opensbi.git/lib/sbi/riscv_atomic.c, branch v1.4Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/opensbi.git/atom/lib/sbi/riscv_atomic.c?h=v1.42023-12-08T08:36:40Zlib: sbi: Replace __atomic_op_bit_ord with __atomic intrinsics2023-12-08T08:36:40ZAnup Patelanup@brainfault.org2023-12-08T08:24:07Zurn:sha1:88398696c816dfc79d5301180dfe42a5d8c497c9
Simplify atomic-related bit operations through __atomic intrinsics.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
lib: sbi: Fix __atomic_op_bit_ord and comments2023-12-08T08:17:31ZXiang Wwxjstz@126.com2023-11-15T14:59:21Zurn:sha1:11bf49b44466b821d0936419caf24befab0a61b7
The original code returns the value of the word before modification.
When modifying the upper 32 bits under RV64, the value returned via
int return will have no meaning. Corrected to return the value of the
bit. And modify the function description.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
lib: sbi: Remove xchg/cmpxchg implemented via lr/sc2023-12-08T05:24:35ZXiang Wwxjstz@126.com2023-11-08T03:28:16Zurn:sha1:6b9a8494828d3983784fb46bb6cd2b6cc9a54ab1
lr/sc is part of the A extension. If the A extension is not supported,
lr/sc cannot be used. So remove xchg/cmpxchg.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
lib: sbi: fix atomic_add_return2021-04-09T13:21:02ZXiang Wwxjstz@126.com2021-04-06T03:34:38Zurn:sha1:70ffc3e2e690f2b7bcea456f49206b636420ef5f
The unsigned length may be 4 bytes or 8 bytes, amoadd.w only applies
to 4 bytes hence this patch.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
include: Use more consistent name for atomic xchg() and cmpxchg()2020-03-28T08:02:38ZAnup Patelanup.patel@wdc.com2020-03-26T12:40:02Zurn:sha1:5b6957eed75ca7842861e0f6765d0f6a64408e05
We should remove the "arch_" prefix from atomic xchg() and cmpxchg()
function names to have consistent naming of all atomic functions.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
lib: sbi: Fix coding style issues2020-03-10T04:57:28ZBin Mengbmeng.cn@gmail.com2020-03-09T03:52:41Zurn:sha1:650c0e525ce60e80b6756aa8cc4eeae5b20ccbd8
This fixes various coding style issues found in the SBI codes.
No functional changes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
include: Move bits related defines and macros to sbi_bitops.h2020-03-08T05:36:18ZAnup Patelanup.patel@wdc.com2020-03-04T05:38:35Zurn:sha1:00d332bbe726d85e4c2b81ab0a08182612f96c03
The right location for all bits related defines and macros is
sbi_bitops.h hence this patch. With this patch, the sbi_bits.h
is redundant so we remove it.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
lib: Fix typo in atomic exchange functions2020-02-22T04:34:38ZAtish Patraatish.patra@wdc.com2020-02-21T23:47:53Zurn:sha1:c3b3b8f43b49e4fa8fde5e916cd8d573687e3626
There is a typo in atomic operations code which prevents the
usage of riscv atomic instructions even if it is supported.
Fix the typo.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
lib: Support atomic swap instructions2019-08-31T07:43:47ZAtish Patraatish.patra@wdc.com2019-08-29T22:19:12Zurn:sha1:6bd1512024c84250a248dea37f30b71a2c4c260f
If compiler supports riscv atomic instructions, we should
use them instead of legacy gcc built-in macros
__sync_lock_test_and_set in atomic exchange functions.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
lib: Provide an atomic exchange function unsigned long2019-08-16T03:12:52ZAtish Patraatish.patra@wdc.com2019-08-15T01:02:13Zurn:sha1:f6e13e0dd30b164eb444bc08c70fa1b8576e0bca
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>