opensbi.git/lib/sbi/riscv_locks.c, branch master

lib: Use proper add opcode on RV32 with Zalrsc

2026-03-10T05:17:23Z

The addw opcode is only defined in RV64, which produces 32-bit results. On RV32, the default add opcode already produces 32-bit results. Fixes: 995f226f3f33 ("lib: Emit lr and sc instructions based on -march flags") Signed-off-by: Marti Alonso Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260301205421.2074835-1-martialonso11@gmail.com Signed-off-by: Anup Patel

lib: atomics: fix AMO test macros

2025-12-28T15:14:03Z

The "RISC-V C API" [1] defines architecture extension test macros says naming rule for the test macros is __riscv_, where is all lower-case. Three extensions dealing with atomics implementation are: "zaamo" consists of AMO instructions, "zalrsc" - LR/SC, "a" extension means both "zaamo" and "zalrsc" Built-in test macros are __riscv_a, __riscv_zaamo and __riscv_zalrsc. Alternative to the __riscv_a macro name, __riscv_atomic, is deprecated. Use correct test macro __riscv_zaamo for the AMO variant of atomics. It used to be __riscv_atomic that is both deprecated and incorrect because it tests for the "a" extension; i.e. both "zaamo" and "zalrsc" If ISA enables only zaamo but not zalrsc, code as it was would not compile. Older toolchains may have neither __riscv_zaamo nor __riscv_zalrsc, so query __riscv_atomic - it should be treated as both __riscv_zaamo and __riscv_zalrsc, in all present cases __riscv_zaamo is more favorable so take is as alternative for __riscv_zaamo [1] https://github.com/riscv-non-isa/riscv-c-api-doc Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251228073321.1533844-1-vladimir.kondratiev@mobileye.com Signed-off-by: Anup Patel

lib: Emit lr and sc instructions based on -march flags

2025-03-28T13:22:05Z

When -march=rv64im_zalrsc_zicsr is used, provide atomic operations and locks using lr and sc instructions only. Signed-off-by: Chao-ying Fu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250226014727.19710-1-cfu@mips.com Signed-off-by: Anup Patel

lib: sbi: Have spinlock checks return bool

2021-05-14T11:35:20Z

spin_lock_check already returned bool in the source file but not in the header. With some toolchains that causes an error, as it should. Because it and related functions all essentially return a bool, we can use this opportunity to change them. Signed-off-by: Daniel Schaefer Reviewed-by: Anup Patel

lib: sbi: Replace test-and-set locks by ticket locks

2021-04-09T13:18:50Z

Replace the test-and-set spinlock implementation with ticket locks in order to get fairness (in form of FIFO order). The implementation uses a 32-bit wide struct, which consists of two 16-bit counters (owner and next). This is inspired by similar spinlock implementations on other architectures. This allows that the code works for both, RV32 and RV64. Signed-off-by: Christoph Muellner Reviewed-by: Anup Patel Reviewed-by: Xiang W

lib: Move sbi core library to lib/sbi

2019-06-19T04:18:51Z

Signed-off-by: Atish Patra Acked-by: Anup Patel