opensbi.git/lib/sbi/sbi_dbtr.c, branch master

lib: sbi: dbtr: do not unconditionally access tdata2/tdata3 CSRs

2026-06-17T04:12:57Z

The current SBI DBTR extension implementation accesses tdata2 and tdata3 without first checking whether either register is implemented on the underlying hart. This produces an illegal instruction exception on otherwise spec-compliant cores that legitimately omit one or both registers. Per the RISC-V Debug Specification, Chapter 5 (Sdtrig ISA Extension) and Section 5.7 (Trigger Module Registers): Section 5 (Sdtrig introduction): "If Sdtrig is implemented, the Trigger Module must support at least one trigger. Accessing trigger CSRs that are not used by any of the implemented triggers must result in an illegal instruction exception. M-Mode and Debug Mode accesses to trigger CSRs that are used by any of the implemented triggers must succeed, regardless of the current type of the currently selected trigger." Section 5.7 (Trigger Module Registers): "Attempts to access an unimplemented Trigger Module Register raise an illegal instruction exception." Per-register optionality is also explicit: Section 5.7.3 (Trigger Data 2, at 0x7a2): "Trigger-specific data. It is optional if no implemented triggers use it." Section 5.7.4 (Trigger Data 3, at 0x7a3): "Trigger-specific data. It is optional if no implemented triggers use it." Section 5.7.17 (Trigger Extra (RV32), at 0x7a3), which also applies via textra64 on RV64: "All functionality in this register is optional. Any number of upper bits of mhvalue and svalue may be tied to 0. mhselect and sselect may only support 0 (ignore)." Unconditionally accessing tdata2/tdata3 in the install/update/read/ uninstall paths causes SBI calls to fail with an illegal instruction exception on hardware that does not implement one or both CSRs, even if the supervisor-supplied trigger configuration does not require the missing CSR(s). This patch: 1. Introduces tdata_read_safe() / tdata_write_safe() helpers that wrap csr_read_allowed / csr_write_allowed so that an illegal- instruction trap raised by an unimplemented CSR is caught locally rather than propagated. On the read path, a trapped read yields zero; on the write path, the trap is silently absorbed (writes to an unimplemented CSR are no-ops by definition). Every tdata2/tdata3 read and write in the install/update/read/uninstall paths is converted to these helpers. 2. On the install and update paths, rejects requests that program a non-zero trig_tdata2 or trig_tdata3 into an unimplemented CSR with SBI_ERR_NOT_SUPPORTED, matching the SBI spec wording in sections 19.4 / 19.5: "One of the trigger configuration can't be programmed due to unimplemented optional bits in tdata1, tdata2, or tdata3 CSRs." Implementation status is probed once per call via the tdata_implemented() helper. This only catches the "whole CSR unimplemented" case; tied-off WARL bits inside an otherwise- implemented CSR are not caught here and would require programming the trigger and reading the value back for comparison, which can be addressed separately. 3. Enable tdata3 configuration in the debug trigger install path. References: - RISC-V Debug Specification, Chapter 5 (Sdtrig), sections 5, 5.7, 5.7.3, 5.7.4, 5.7.17. - RISC-V SBI Specification v3.0, Chapter 19 (Debug Triggers Extension), sections 19.4, 19.5. Fixes: 97f234f15c96 ("lib: sbi: Introduce the SBI debug triggers extension support") Suggested-by: Nicholas Piggin Suggested-by: Himanshu Chauhan Signed-off-by: David E. Garcia Porras Reviewed-By: Himanshu Chauhan Link: https://lore.kernel.org/r/20260616170118.3515676-1-david.garcia@aheadcomputing.com Signed-off-by: Anup Patel

lib: sbi: Replace sbi_hart_pmp_xyz() and sbi_hart_map/unmap_addr()

2025-12-16T14:46:47Z

The sbi_hart_pmp_xyz() and sbi_hart_map/unmap_addr() functions can now be replaced by various sbi_hart_protection_xyz() functions. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20251209135235.423391-5-apatel@ventanamicro.com Signed-off-by: Anup Patel

dbtr: Fix sbi_dbtr_read_trig to read from CSRs

2025-08-28T05:20:14Z

sbi_dbtr_read_trig returned the saved state of tdata{1-3}, when it should have returned the updated state read from CSRs. Update sbi_dbtr_read_trig to return updated state read from CSRs. Signed-off-by: Anup Patel Signed-off-by: Jesse Taube Link: https://lore.kernel.org/r/20250811152947.851208-1-jesse@rivosinc.com Signed-off-by: Anup Patel

dbtr: Add support for icount trigger type

2025-08-28T05:06:52Z

The linux kernel needs icount to implement hardware breakpoints. Signed-off-by: Jesse Taube Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250724183120.1822667-1-jesse@rivosinc.com Signed-off-by: Anup Patel

lib: sbi: dbtr: Fix update_triggers to match SBI

2025-06-16T11:31:52Z

OpenSBI implements sbi_dbtr_update_trig as `sbi_dbtr_update_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)` yet SBI v3.0-rc7 Chapter 19. Debug Triggers Extension [0] declares it as `sbi_debug_update_triggers(unsigned long trig_count)` Change update_triggers to match SBI. [0] https://github.com/riscv-non-isa/riscv-sbi-doc/tree/v3.0-rc7/src/ext-debug-triggers.adoc Fixes: 97f234f15c96 ("lib: sbi: Introduce the SBI debug triggers extension support") Signed-off-by: Jesse Taube Reviewed-by: Himanshu Chauhan Tested-by: Charlie Jenkins Reviewed-by: Charlie Jenkins Link: https://lore.kernel.org/r/20250528154604.571815-1-jesse@rivosinc.com Signed-off-by: Anup Patel

lib: sbi: Optimize saddr mapping in sbi_dbtr.c

2025-06-16T11:23:50Z

The original implementation mapped saddr individually for each entry. The updated code now maps saddr for all entries in a single operation. This change reduces the number of PMP (Physical Memory Protection) operations, improving efficiency and performance. Tested-by: Himanshu Chauhan Reviewed-by: Himanshu Chauhan Signed-off-by: Xiang W Link: https://lore.kernel.org/r/20250514052422.575551-1-wxjstz@126.com Signed-off-by: Anup Patel

lib: sbi: dbtr: Fix shared memory layout

2025-06-16T04:44:20Z

The existing sbi_dbtr_shmem_entry has a size of 5 * XLEN with the final entry being idx. This is in contrast to the SBI v3.0-rc7 Chapter 19. Debug Triggers Extension [0] where idx and trig_state share the same offset (0) in shared memory, with a total size of 4 * XLEN for all the SBI calls. Replace struct with union to match memory layout described in SBI. [0] https://github.com/riscv-non-isa/riscv-sbi-doc/tree/v3.0-rc7/src/ext-debug-triggers.adoc Fixes: 97f234f15c96 ("lib: sbi: Introduce the SBI debug triggers extension support") Signed-off-by: Jesse Taube Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins Reviewed-by: Himanshu Chauhan Tested-by: Himanshu Chauhan Link: https://lore.kernel.org/r/20250604135225.842241-1-jesse@rivosinc.com Signed-off-by: Anup Patel

lib: sbi: Update sbi_domain_is_assigned_hart() to take a hart index

2024-09-26T10:59:25Z

This removes redundant hartid to hartindex conversions from four call sites and provides a net reduction in code size. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel

lib: Delete redundant `ulong`

2024-08-24T09:12:14Z

In `csr_read_allowed` and `csr_write_allowed` macros, has already converted second param to `ulong`. So delete redundant `ulong` where uses csr_read/write_allowed macros. Signed-off-by: Zhang RunMin Reviewed-by: Anup Patel

lib: sbi: dbtr: fix potential NULL pointer dereferences

2024-08-02T03:15:05Z

In several dbtr functions, we first check that the dbtr trigger is not NULL and that its state is what we expect. However, it only makes sense to perform the second check if the dbtr trigger is not NULL. Othwerwise we will dereference a NULL pointer. Thus, change the condition so that it shortcuts to the first check if necessary. Signed-off-by: Carlos López Reviewed-By: Anup Patel