opensbi.git/lib/sbi/sbi_domain_context.c, branch master

lib: sbi: Add domain parameter to hart protection (un)configure()

2026-08-02T09:47:12Z

The switch_to_next_domain_context() already has the pointers to current and next domains so pass them as parameters to hart protection configure() and unconfigure() callbacks. Signed-off-by: Anup Patel Reviewed-by: Rahul Pathak Link: https://lore.kernel.org/r/20260727042504.1743250-4-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi: Introduce sbi_hart_protection_reconfigure() function

2026-08-02T09:47:12Z

Instead of assuming that hart protection reconfiguration is unconfigure followed by configure, introduce a separate sbi_hart_protection_reconfigure() function and use it in switch_to_next_domain_context(). Signed-off-by: Anup Patel Reviewed-by: Rahul Pathak Link: https://lore.kernel.org/r/20260727042504.1743250-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_domain_context: Flush TLB after SATP mode switch

2026-06-09T16:42:48Z

When switching between domains with different satp.MODE values (e.g. Sv39 to Sv48), the RISC-V ISA permits hardware to use cached translations from the old virtual-address width if no SFENCE.VMA intervenes. This constrained-unpredictable behavior is clarified in riscv-isa-manual PR #2219. The hart protection re-configuration will anyway do full SFENCE / HFENCE so move the hart protection re-configuration after register context switch in switch_to_next_domain_context() to ensure translations from the new domain's address width are used. Link: https://github.com/riscv/riscv-isa-manual/pull/2219 Signed-off-by: Zishun Yi Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260429181747.160033-1-vulab@iscas.ac.cn Signed-off-by: Anup Patel

lib: sbi: domain FP/Vector context support for context switch

2026-05-18T08:32:28Z

This patch adds proper support for per-domain floating-point (FP) and vector (V) contexts in the domain context switch logic. Each domain now maintains its own FP and vector state, which is saved and restored during domain switches. Conditionalize FP and Vector save/restore based on extensions, unconditional save and restore of floating-point (FP) and Vector registers fails on generic platform firmware. This firmware must run on multiple platforms that may lack these extensions. Address this by conditionally executing FP save/restore only if the underlying hart supports the F or D extensions. Similarly, perform Vector save/restore only if the hart supports the Vector extension. This improves support for multi-domain systems with FP and Vector extensions, and prevents corruption of FP/Vector state during domain switches. Signed-off-by: Dave Patel Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260518083023.997323-4-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi: Replace sbi_hart_pmp_xyz() and sbi_hart_map/unmap_addr()

2025-12-16T14:46:47Z

The sbi_hart_pmp_xyz() and sbi_hart_map/unmap_addr() functions can now be replaced by various sbi_hart_protection_xyz() functions. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20251209135235.423391-5-apatel@ventanamicro.com Signed-off-by: Anup Patel

lib: sbi: Introduce sbi_hart_pmp_unconfigure() function

2025-12-16T14:46:47Z

Currently, the unconfiguring PMP is implemented directly inside switch_to_next_domain_context() whereas rest of the PMP programming is done via functions implemented in sbi_hart.c. Introduce a separate sbi_hart_pmp_unconfigure() function so that all PMP programming is in one place. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20251209135235.423391-2-apatel@ventanamicro.com Signed-off-by: Anup Patel

lib: sbi: Enable Ssqosid Ext using mstateen0

2025-12-08T05:34:06Z

The QoS Identifiers extension (Ssqosid) introduces the srmcfg register, which configures a hart with two identifiers: a Resource Control ID (RCID) and a Monitoring Counter ID (MCID). These identifiers accompany each request issued by the hart to shared resource controllers. If extension Smstateen is implemented together with Ssqosid, then Ssqosid also requires the SRMCFG bit in mstateen0 to be implemented. If mstateen0.SRMCFG is 0, attempts to access srmcfg in privilege modes less privileged than M-mode raise an illegal-instruction exception. If mstateen0.SRMCFG is 1 or if extension Smstateen is not implemented, attempts to access srmcfg when V=1 raise a virtual-instruction exception. This extension can be found in the RISC-V Instruction Set Manual: https://github.com/riscv/riscv-isa-manual Changes in v5: - Remove SBI_HART_EXT_SSQOSID dependency SBI_HART_PRIV_VER_1_12 Changes in v4: - Remove extraneous parentheses around SMSTATEEN0_SRMCFG Changes in v3: - Check SBI_HART_EXT_SSQOSID when swapping SRMCFG Changes in v2: - Remove trap-n-detect - Context switch CSR_SRMCFG Signed-off-by: Chen Pei Reviewed-by: Radim Krčmář Link: https://lore.kernel.org/r/20251114115722.1831-1-cp0613@linux.alibaba.com Signed-off-by: Anup Patel

lib: sbi_domain_context: preserve firmware PMP entries during domain context switch

2025-11-02T11:30:49Z

When SmePMP is enabled, clearing firmware PMP entries during a domain context switch can temporarily revoke access to OpenSBI’s own code and data, leading to faults. Keep firmware PMP entries enabled across switches so firmware regions remain accessible and executable. Signed-off-by: Yu-Chien Peter Lin Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251008084444.3525615-9-peter.lin@sifive.com Signed-off-by: Anup Patel

lib: sbi: Prevent target domain same as the current

2025-10-06T09:01:52Z

Add error handling code to sbi_domain_context_enter to prevent the target domain from being the same as the current domain. Signed-off-by: Xiang W Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250903044619.394019-4-wxjstz@126.com Signed-off-by: Anup Patel

lib: sbi: Add hart context init when first call enter

2025-10-06T09:01:48Z

When entering sbi_domain_context_enter for the first time, the hart context may not be initialized. Add initialization code. Signed-off-by: Xiang W Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250903044619.394019-3-wxjstz@126.com Signed-off-by: Anup Patel