opensbi.git/lib/sbi/sbi_irqchip.c, branch master

lib: sbi_irqchip: fix MSI EIID gap and tail allocation logic in register_msi

2026-07-22T07:50:22Z

Fix sbi_irqchip_register_msi() that prevented contiguous EIID allocation: - Gap check condition was inverted: the original `h->first_hwirq - hwirq < num_hwirq` incorrectly set `found = true` when the gap was too small to fit num_hwirq entries. Correct to `>= num_hwirq` so allocation only proceeds when sufficient space exists between registered handlers. - Tail-space check `!found && !hwirq` never triggered after iteration Replace with `(chip->num_hwirq - hwirq) >= num_hwirq` to correctly allocate if handler list is empty. Fixes: 79e63bc8348d ("irqchip: add sbi_irqchip_register_msi support") Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-7-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/imsic: track IRQ enable state and restore EIE on warm init

2026-07-22T07:50:20Z

Add an irq_state field to struct sbi_irqchip_hwirq_data with a single IRQ_ENABLED flag (bit 0) to track whether a hardware interrupt has been enabled via the irqchip framework. Set IRQ_ENABLED in sbi_irqchip_unmask_hwirq() when the unmask callback is invoked. Add sbi_irqchip_get_irq_state() as a private inline accessor and expose sbi_irqchip_is_irq_enabled() as a public API for drivers to query the enabled state of a hardware interrupt by chip pointer and hwirq number. Refactor imsic_local_eix_update() to operate on a single interrupt ID instead of a base+count range, simplifying the CSR bit manipulation to a direct BIT(id) write without the inner loop. Update all call sites accordingly. Use sbi_irqchip_is_irq_enabled() in imsic_warm_irqchip_init() to restore per-EIID EIE CSR state on warm boot and HSM resume based on the saved irq_state, replacing the previous blanket disable of all interrupts. This ensures that EIIDs enabled during hotplug/warminit cycle are correctly re-enabled on the resuming hart without requiring software to re-register or re-unmask each interrupt. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-6-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/aplic: add MSI mode support with IMSIC parent linking

2026-07-22T07:38:13Z

Add parent_unique_id fields to struct aplic_data for IMSIC parent linking in MSI mode. Store parent IMSIC unique_id during FDT parsing of the APLIC node. Add aplic_is_msi_mode() complementing aplic_is_direct_mode() to consolidate delivery mode detection. Add APLIC_TARGET_EIID() macro for packing the EIID field into the TARGET register. Add parent_unique_id and parent_irq_map fields to struct aplic_data. parent_unique_id identifies the upstream IMSIC irqchip device resolved via sbi_irqchip_find_device() during hwirq_setup. parent_irq_map is a per-source array allocated at cold init time to track the EIID assigned by the IMSIC for each APLIC source. Restore aplic_writel_msicfg() and re-introduce MSI address register programming in aplic_init(), gated on aplic_is_msi_mode(). Set the DOMAINCFG_DM bit to switch the hardware to MSI delivery mode when no IDC structures are present. Add aplic_program_msi_target() to pack hart_index, guest_index, and EIID into the APLIC_TARGET register. Add aplic_write_msi() as the sbi_irqchip write_msi callback that extracts EIID and hart_index from the MSI message and calls aplic_program_msi_target(). Add aplic_msi_callback() as the MSI receive callback that dispatches to sbi_irqchip_process_hwirq() on the APLIC chip. Extend aplic_hwirq_setup() with an MSI path that resolves the parent IMSIC chip by parent_unique_id, registers an MSI route via sbi_irqchip_register_msi(), and stores the allocated EIID in parent_irq_map for the source being configured. Extend aplic_hwirq_set_affinity() with an MSI path that delegates affinity reprogramming to the parent IMSIC chip via sbi_irqchip_set_affinity() using the stored parent_irq_map entry. Guard warm_init, process_hwirqs, and hwirq_eoi with early returns in MSI mode as interrupt delivery and acknowledgement are handled by the IMSIC in that configuration. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-3-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: fix device lookup by caps when first is NULL

2026-07-16T05:57:57Z

When called with first == NULL, sbi_irqchip_find_device_by_caps() should scan the device list from the start. Instead it always returns NULL: "found" starts false and only flips true when an entry equals "first", but no entry ever equals NULL, so every entry hits "else continue" and nothing is checked. This breaks MSI detection in sbi_mpxy, which calls it with first == NULL: ms->msi_avail = !!sbi_irqchip_find_device_by_caps(SBI_IRQCHIP_CAPS_MSI, NULL); msi_avail is therefore always false, so mpxy_write_std_attr() silently drops the MSI attributes (MSI_ADDR_LO/HI, MSI_DATA, MSI_CONTROL) while still returning success, and MSI-based MPXY notifications are never delivered. Initialize "found" from "first" so a NULL "first" scans from the beginning, and always continue in the pre-match branch so a non-NULL "first" resumes after the given device. Fixes: 8570b938444d ("lib: sbi_irqchip: Allow irqchip drivers advertise capabilities") Signed-off-by: David E. Garcia Porras Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260701181334.969877-1-david.garcia@aheadcomputing.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Allow irqchip drivers advertise capabilities

2026-06-10T12:43:10Z

Extend struct sbi_irqchip_device to allow irqchip drivers advertise interrupt controller capabilities (such as wired interrupt, MSIs, etc). This further allows other parts of OpenSBI to lookup irqchip devices based on capabilities. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260608125257.3220114-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Add support for registering MSI handlers

2026-05-12T04:25:58Z

Some of the drivers (such as APLIC) require capability to registers MSI handlers from the parent interrupt controller (such as IMSIC) so add sbi_irqchip_register_msi_handler() for this purpose. Link: https://lore.kernel.org/r/20260423052339.356900-7-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Allow setting hardware interrupt affinity

2026-05-12T04:25:58Z

The irqchip drivers can provide mechanism to set interrupt affinity so add hwirq_set_affinity() callback for irqchip drivers and use it to implement sbi_irqchip_set_affinity() which can be used by other drivers. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260423052339.356900-6-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Allow marking hardware interrupts as reserved

2026-05-12T04:25:58Z

Some of the hardware interrupts may be special so allow irqchip drivers to make these hardware interrupts as reserved. Introduce sbi_irqchip_register_reserved() for this purpose. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260423052339.356900-5-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Allow interrupt client to specify line sensing

2026-05-12T04:25:58Z

The interrupt client should be allowed to specify the line sensing type of the hwirqs for which it is registering handler. To support this, add hwirq_flags parameter to hwirq_setup() callback provided by the irqchip driver. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260423052339.356900-4-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Keep the handler list in sorted order for irqchip

2026-05-12T04:25:58Z

Let's keep the handler list in sorted order for irqchip so that it is easier to allocate unused hardware interrupts based on the sorted list. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260423052339.356900-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel