opensbi.git/lib/sbi/sbi_misaligned_ldst.c, branch v0.7

lib: sbi_misaligned_ldst: Remove mcause, scratch and hartid parameters

2020-03-28T08:02:14Z

We remove mcause, scratch and hartid parameters from various functions for misaligned load/store handling because we can always get current HART id and current scratch pointer using just one CSR access. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi_trap: Remove scratch parameter from sbi_trap_redirect()

2020-03-28T08:02:04Z

The scratch parameter of sbi_trap_redirect() is not used hence we remove it. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: Remove scratch parameter from unpriv load/store functions

2020-03-28T08:02:01Z

The scratch parameter of unpriv load/store functions is now redundant hence we remove it. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi: Fix misaligned trap handling

2020-03-13T04:32:42Z

Compile time checks of __riscv_compressed can only check if OpenSBI is being compiled using compressed instructions or not. Checking this macro does not indicate if an instruction that generated a misaligned trap is a compressed instruction or not. Since the misaligned trap handling code inspects instructions _C_ bits to detect compressed instructions, we can remove all static checks on __riscv_compressed and dissociate hanlding of misaligned traps and OpenSBI compilation. Signed-off-by: Damien Le Moal Reviewed-by: Bin Meng Reviewed-by: Anup Patel

lib: Use MTINST CSR in misaligned load/store emulation

2019-12-16T09:18:31Z

We should use MTINST CSR in misaligned load/store emulation whenever possible to avoid unpriv read in getting trapped instruction. This will improve preformance on HW having proper implementation of MTINST CSR. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis

lib: Extend trap redirection for hypervisor v0.5 spec

2019-12-16T09:18:26Z

The hypervisor v0.5 spec introduces two new CSRs for both M-mode and HS-mode which need to be considered when redirecting traps hence this patch. Signed-off-by: Anup Patel

lib: Better naming of unpriv APIs for wider use

2019-11-21T08:27:33Z

The unpriv APIs can be useful to external firmware and out-of-tree platform support code. This patch adds "sbi_" prefix to unpriv load/store APIs and rename struct riscv_unpriv to struct sbi_trap_info everywhere. We also place struct sbi_trap_info in sbi/sbi_trap.h so that we can use it for sbi_trap_redirect() as well. Overall, this patch will make naming of unpriv APIs consistent with other OpenSBI APIs. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: No need to set VSSTATUS.MXR bit in get_insn()

2019-11-21T08:26:03Z

We don't need to set VSSTATUS.MXR bit in get_insn() for unpriv instruction read because MSTATUS.MXR bit applies to both "Stage1" and "Stage2" page tables. This also allows us to remove the "virt" parameter of get_insn() function. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

include: Extend get_insn() to read instruction from VS/VU mode

2019-09-30T10:05:43Z

Current implementation of get_insn() is not suitable for reading instruction from VS/VU mode because we have to set SSTATUS_MXR bit in VSSTATUS CSR for reading instruction from VS/VU mode. This patch extends get_insn() to read instruction from VS/VU mode. Signed-off-by: Anup Patel Signed-off-by: Alistair Francis

lib: Handle traps when doing unpriv load/store in get_insn()

2019-08-13T04:18:40Z

We can get a page/access trap when doing unpriv load/store in get_insn() function because on a SMP system Linux swapper running on HART A can unmap pages from page table used by HART B. To tackle this we extend get_insn() implementation so that if we get trap in get_insn() then we redirect it to S-mode as fetch page/access fault. Signed-off-by: Anup Patel