opensbi.git/lib/sbi/sbi_misaligned_ldst.c, branch v1.0

lib: sbi: Implement firmware counters

2021-07-11T05:08:23Z

RISC-V SBI v0.3 specification defines a set of firmware events that can provide additional information about the current firmware context. All of the firmware event monitoring are enabled now. The firmware events must be defined as raw perf event with MSB set as specified in the specification. Reviewed-by: Anup Patel Signed-off-by: Atish Patra

lib: sbi: Fix sign-extension in sbi_misaligned_load_handler()

2020-12-24T11:05:28Z

The misaligned load emulation does not sign-extend values correctly due to missing sign typecast in value passed to the SET_RD() macro. A very easy way to reproduce this issue is to load 16-bit value 0xff1e from a byte aligned address using LH instruction on hardware lacking misaligned load/store. This patch fixes sbi_misaligned_load_handler() for above issue. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi_misaligned_ldst: Determine transformed instruction length correctly

2020-08-04T03:18:41Z

If MTINST[0:0] bit is 1 then we have transformed instruction encoding in MTINST CSR. For transformed instructions, if the MTINST[1:1] bit is Zero then original trapped instruction was a 16bit instruction which was converted to 32bit instruction at time of taking trap. We should use MTINST[1:1] bit to determine correct instruction length of transformed instruction. This patch updates misaligned load/store emulation as-per above. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi_misaligned_ldst: Remove mcause, scratch and hartid parameters

2020-03-28T08:02:14Z

We remove mcause, scratch and hartid parameters from various functions for misaligned load/store handling because we can always get current HART id and current scratch pointer using just one CSR access. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi_trap: Remove scratch parameter from sbi_trap_redirect()

2020-03-28T08:02:04Z

The scratch parameter of sbi_trap_redirect() is not used hence we remove it. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: Remove scratch parameter from unpriv load/store functions

2020-03-28T08:02:01Z

The scratch parameter of unpriv load/store functions is now redundant hence we remove it. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi: Fix misaligned trap handling

2020-03-13T04:32:42Z

Compile time checks of __riscv_compressed can only check if OpenSBI is being compiled using compressed instructions or not. Checking this macro does not indicate if an instruction that generated a misaligned trap is a compressed instruction or not. Since the misaligned trap handling code inspects instructions _C_ bits to detect compressed instructions, we can remove all static checks on __riscv_compressed and dissociate hanlding of misaligned traps and OpenSBI compilation. Signed-off-by: Damien Le Moal Reviewed-by: Bin Meng Reviewed-by: Anup Patel

lib: Use MTINST CSR in misaligned load/store emulation

2019-12-16T09:18:31Z

We should use MTINST CSR in misaligned load/store emulation whenever possible to avoid unpriv read in getting trapped instruction. This will improve preformance on HW having proper implementation of MTINST CSR. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis

lib: Extend trap redirection for hypervisor v0.5 spec

2019-12-16T09:18:26Z

The hypervisor v0.5 spec introduces two new CSRs for both M-mode and HS-mode which need to be considered when redirecting traps hence this patch. Signed-off-by: Anup Patel

lib: Better naming of unpriv APIs for wider use

2019-11-21T08:27:33Z

The unpriv APIs can be useful to external firmware and out-of-tree platform support code. This patch adds "sbi_" prefix to unpriv load/store APIs and rename struct riscv_unpriv to struct sbi_trap_info everywhere. We also place struct sbi_trap_info in sbi/sbi_trap.h so that we can use it for sbi_trap_redirect() as well. Overall, this patch will make naming of unpriv APIs consistent with other OpenSBI APIs. Signed-off-by: Anup Patel Reviewed-by: Atish Patra