<feed xmlns='http://www.w3.org/2005/Atom'>
<title>opensbi.git/lib/sbi/sbi_timer.c, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/lib/sbi/sbi_timer.c?h=master</id>
<link rel='self' href='http://cgit.235523.xyz/opensbi.git/atom/lib/sbi/sbi_timer.c?h=master'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/'/>
<updated>2026-05-09T07:46:07Z</updated>
<entry>
<title>lib: sbi_timer: Introduce sbi_timer_compute_delta() and friends</title>
<updated>2026-05-09T07:46:07Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-04-25T10:40:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=1932ee3f0ae2f200431c20018e2d75dbceb65695'/>
<id>urn:sha1:1932ee3f0ae2f200431c20018e2d75dbceb65695</id>
<content type='text'>
The users of timer event have to compute next_event (aka timer value
in the future) based on desired units and unit frequency. Introduce
sbi_timer_compute_delta() and friends to simplify computing next_event
for timer event users.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Reviewed-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
Link: https://lore.kernel.org/r/20260425104048.2335262-5-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_timer: Add support for timer events</title>
<updated>2026-05-09T07:46:05Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-04-25T10:40:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=b7fa8a246cba80d74c0993dd0275b3c1589ef8b6'/>
<id>urn:sha1:b7fa8a246cba80d74c0993dd0275b3c1589ef8b6</id>
<content type='text'>
Currently, the sbi_timer only supports timer events configured via
SBI calls. Introduce struct sbi_timer_event and related functions
to allow configuring timer events from any part of OpenSBI.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Reviewed-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
Link: https://lore.kernel.org/r/20260425104048.2335262-4-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_timer: Introduce per-HART timer state</title>
<updated>2026-05-09T07:45:43Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-04-25T10:40:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=357fae4820718f633abeb7aa6ca00fd57a574d8d'/>
<id>urn:sha1:357fae4820718f633abeb7aa6ca00fd57a574d8d</id>
<content type='text'>
Currently, only time_delta is per-HART so introduce per-HART timer
state for having more per-HART timer information.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Reviewed-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
Link: https://lore.kernel.org/r/20260425104048.2335262-3-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: hart: Detect existence of cycle and instret CSRs for Zicntr</title>
<updated>2025-05-20T07:55:53Z</updated>
<author>
<name>Yao Zi</name>
<email>ziyao@disroot.org</email>
</author>
<published>2025-05-16T13:33:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=7e31dc80525f752d97c2c5a97eb4b9583054e8bc'/>
<id>urn:sha1:7e31dc80525f752d97c2c5a97eb4b9583054e8bc</id>
<content type='text'>
Zicntr extension specifies three read-only CSRs, time, cycle and
instret. It isn't sufficient to report Zicntr is fully supported with
only time CSR detected.

This patch introduces a bitmap to sbi_hart_features to record
availability of these CSRs, which are detected using traps. Zicntr is
reported as present if and only if three CSRs are all available on the
HARTs.

Sites originally depending on SBI_HART_EXT_ZICNTR for detecting
existence of time CSR are switched to detect SBI_HART_CSR_TIME instead.

Suggested-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Yao Zi &lt;ziyao@disroot.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250516133352.36617-3-ziyao@disroot.org
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: use 64 bit csr macros</title>
<updated>2025-04-30T04:44:25Z</updated>
<author>
<name>Radim Krčmář</name>
<email>rkrcmar@ventanamicro.com</email>
</author>
<published>2025-04-29T14:25:44Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=65e8be4fe85e0e4410026a86256682a314ddf173'/>
<id>urn:sha1:65e8be4fe85e0e4410026a86256682a314ddf173</id>
<content type='text'>
Switch the most obvious cases to new macros.

Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Radim Krčmář &lt;rkrcmar@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20250429142549.3673976-4-rkrcmar@ventanamicro.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: Drop timer warm init and exit hooks</title>
<updated>2024-11-05T12:09:31Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-09-03T04:06:50Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=99b01ab610acf6ff7c3d0199f13f5b41322a22e2'/>
<id>urn:sha1:99b01ab610acf6ff7c3d0199f13f5b41322a22e2</id>
<content type='text'>
Now that driver lifecycle is managed from within the SBI timer core,
platforms need only to initialize the driver once during cold init.
Remove the remaining platform hooks that are no longer used.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_timer: Call driver warm_init from SBI core</title>
<updated>2024-11-05T11:59:13Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-09-03T04:06:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=450082874346bb25109877b7ac6a1754f089f538'/>
<id>urn:sha1:450082874346bb25109877b7ac6a1754f089f538</id>
<content type='text'>
Currently, the platform's timer device is tracked in two places: the
core SBI implementation has `timer_dev`, and the FDT timer layer has
`current_driver`. The latter is used for warm initialization of the
timer device. However, this warm init is not specific to FDT-based
platforms; other platforms call exactly the same functions from the
same point in the boot sequence.

The code is simplified and made common across platforms by treating warm
init and exit as properties of the driver, not the platform. Then the
platform's only role is to select and prepare a driver during cold boot.

For now, only add a .warm_init hook, since none of the existing drivers
need an .exit hook. It could be added in the future if needed.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Fix writes to emulated 32-bit htimedelta CSR</title>
<updated>2024-09-20T16:22:06Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-08-29T20:08:10Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=ebfaf1974e5bb172343ed42a9836e0d5048e3677'/>
<id>urn:sha1:ebfaf1974e5bb172343ed42a9836e0d5048e3677</id>
<content type='text'>
Writes to the low half CSR should not affect the high half of the value.
Make this separation explicit by writing to the delta in memory as two
adjacent XLEN-sized values.

Fixes: 1e9f88889f8b ("lib: Emulate HTIMEDELTA CSR for platforms not having TIME CSR")
Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add Zicntr as a HART ISA extension</title>
<updated>2023-07-09T05:36:24Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-07-05T06:27:17Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=1a398d9faa60ac0341614f59b864340fc5e49a35'/>
<id>urn:sha1:1a398d9faa60ac0341614f59b864340fc5e49a35</id>
<content type='text'>
Recently ratified Zicntr ISA extension covers cycle, time and
instret CSRs so we replace the "time" ISA extension with "zicntr"
ISA extension in OpenSBI.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi_timer: Added a conditional wait function which can timeout</title>
<updated>2022-07-08T09:21:24Z</updated>
<author>
<name>Adnan Rahman Chowdhury</name>
<email>adnan.chowdhury@sifive.com</email>
</author>
<published>2022-06-30T09:46:35Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=994c8cfb29d0b53bbcc774a728cad778aeece6ac'/>
<id>urn:sha1:994c8cfb29d0b53bbcc774a728cad778aeece6ac</id>
<content type='text'>
Motivation: Suppose a peripheral needs to be configured to transmit
data. There is an SFR bit which indicates that the peripheral is ready
to transmit. The firmware should check the bit and will only transmit
data when the peripheral is ready. When the firmware starts polling the
SFR, the peripheral could be busy transmitting/receiving other data so
the firmware must wait till that completes. Assuming that there is no
other way, the firmware shouldn't wait indefinitely.

The function sbi_timer_waitms_until() will constantly check whether a
certain condition is satisfied, or timeout occurs. It can be used for
the cases when a timeout is required.

Signed-off-by: Adnan Rahman Chowdhury &lt;adnan.chowdhury@sifive.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
</feed>
