<feed xmlns='http://www.w3.org/2005/Atom'>
<title>opensbi.git/lib/sbi/sbi_trap.c, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/lib/sbi/sbi_trap.c?h=master</id>
<link rel='self' href='http://cgit.235523.xyz/opensbi.git/atom/lib/sbi/sbi_trap.c?h=master'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/'/>
<updated>2026-07-21T06:20:46Z</updated>
<entry>
<title>lib: sbi: Move trap delegation setup to sbi_trap.c</title>
<updated>2026-07-21T06:20:46Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-06-13T13:21:28Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=c504877ed00bd7c38168a6574db25562e3615a38'/>
<id>urn:sha1:c504877ed00bd7c38168a6574db25562e3615a38</id>
<content type='text'>
Currently, the trap delegation setup is part of sbi_hart.c and
called via sbi_hart_init() whereas the per-hart trap (aka exception
and interrupt) handling is part of sbi_trap.c.

Move trap delegation init to sbi_trap.c and call it via new
sbi_trap_init() from both cold boot and warm boot path. This
way trap delegation setup is in same place as trap handling.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260613132129.2135128-2-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>firmware: Add RNMI handler infrastructure</title>
<updated>2026-05-09T07:29:43Z</updated>
<author>
<name>Evgeny Voevodin</name>
<email>evvoevod@tenstorrent.com</email>
</author>
<published>2026-05-07T18:08:04Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=00fec20b4976c756ddacedef23a6bf510fa00dad'/>
<id>urn:sha1:00fec20b4976c756ddacedef23a6bf510fa00dad</id>
<content type='text'>
Implement basic Resumable NMI (RNMI) handler support for the RISC-V
Smrnmi extension.

The new _trap_rnmi_handler assembly entry point saves context using the
Smrnmi MN* CSRs (MNSCRATCH, MNEPC, MNSTATUS, MNCAUSE) and returns via
mnret. It dispatches to sbi_trap_rnmi_handler(), which optionally calls
a platform-specific ops-&gt;rnmi_handler callback for actual NMI
processing. If no platform handler is registered or it fails, the
event is reported as an unhandled NMI.

The RNMI handler reuses the generic trap context structure but stores MN*
CSR values (MNEPC, MNSTATUS, MNCAUSE) into the corresponding generic
fields (mepc, mstatus, cause) for compatibility with existing trap
infrastructure.

Signed-off-by: Evgeny Voevodin &lt;evvoevod@tenstorrent.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/050ae6d2762ba8d5b9dfb3cc1960a23aa3d6c549.1778176768.git.evvoevod@tenstorrent.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_trap: Add support for vectored interrupts</title>
<updated>2025-04-13T00:21:17Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2025-03-05T01:45:43Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=afa0e3091bebf2aaba167f37119a9a4f608a55a8'/>
<id>urn:sha1:afa0e3091bebf2aaba167f37119a9a4f608a55a8</id>
<content type='text'>
When redirecting an exception to S-mode, transform the (v)stvec CSR
value as described in the privileged spec to derive the S-mode PC.
Since OpenSBI never redirects interrupts, only synchronous exceptions,
the only action needed is to mask out the (v)stvec.MODE field.

Reported-by: Jan Reinhard &lt;jan.reinhard@sysgo.com&gt;
Closes: https://github.com/riscv-software-src/opensbi/issues/391
Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviwed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250305014729.3143535-1-samuel.holland@sifive.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: move sbi_double_trap_handler() to a dedicated header</title>
<updated>2025-01-30T05:02:18Z</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2025-01-10T13:15:51Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=9d2c9c6ca0a56b30379d4993ffcf8d707bd4a8ea'/>
<id>urn:sha1:9d2c9c6ca0a56b30379d4993ffcf8d707bd4a8ea</id>
<content type='text'>
We will add new functions to sbi_double_trap.c in order to register an
SSE event, split this to a header as part of preparation work.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: pmu: fix usage of sbi_pmu_irq_bit()</title>
<updated>2025-01-30T05:00:45Z</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2025-01-10T13:15:50Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=3943ddbaab00247b391128ae0a1f9258d4007f4f'/>
<id>urn:sha1:3943ddbaab00247b391128ae0a1f9258d4007f4f</id>
<content type='text'>
While sbi_pmu_irq_bit() was used to delegate irq to S-mode, LCOFIP usage
was still hardcoded in various places. This led to change the returned
value of sbi_pmu_irq_bit() to be a bit number rather than a bit mask
since it returns an 'int' and we need to obtain the bit number itself to
handle it in the IRQs handlers. Add a similar function to return the
irq mask which can also be used where the mask is required rather than
the bit itself.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: add Ssdbltrp ISA extension support</title>
<updated>2024-10-25T18:28:00Z</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2024-10-18T08:40:04Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=9c7859326909c8025bf23909f1952ee963a1cdd4'/>
<id>urn:sha1:9c7859326909c8025bf23909f1952ee963a1cdd4</id>
<content type='text'>
Add Ssdbltrp trap handler support for S-mode double trap handling. If
the trap is received while in VS-mode, then the trap is redirected to
S-mode. If caught while in HS-mode, then an error is returned to the top
trap handler which will panic.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: factorize previous mode computation</title>
<updated>2024-10-25T18:23:18Z</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2024-10-18T08:40:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=80656bdb1daf380b5562cba11f43754fe916d631'/>
<id>urn:sha1:80656bdb1daf380b5562cba11f43754fe916d631</id>
<content type='text'>
Previous privilege mode retrieval from mstatus is done at different
places, factorize it rather than copy/pasting it again.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: factorize previous virtualization mode read from regs</title>
<updated>2024-10-25T18:22:51Z</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2024-10-18T08:40:02Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=daa282573ffac0f295de7631c98840668f20a568'/>
<id>urn:sha1:daa282573ffac0f295de7631c98840668f20a568</id>
<content type='text'>
The same pattern is used at multiple places to verify in which mode
the exception was actually taken. Factorize it.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: add zicfilp/zicfiss and elp cfi state reflect back in status</title>
<updated>2024-09-23T13:28:04Z</updated>
<author>
<name>Deepak Gupta</name>
<email>debug@rivosinc.com</email>
</author>
<published>2024-09-16T18:23:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=c0804ed49a6ef1d2b757a97baf3f802fd98ae517'/>
<id>urn:sha1:c0804ed49a6ef1d2b757a97baf3f802fd98ae517</id>
<content type='text'>
This patch adds support to check for zicfilp / zicfiss extension.

zicfilp record status of hart's ELP state in *status csr. Missing landing
pad sets MPELP in mstatus. When SBI is redirecting back to S/VS/HS, SPELP
is set in sstatus/vsstatus.

Signed-off-by: Deepak Gupta &lt;debug@rivosinc.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add SSE support for PMU events</title>
<updated>2024-04-05T11:39:39Z</updated>
<author>
<name>Clément Léger</name>
<email>cleger@rivosinc.com</email>
</author>
<published>2024-03-21T15:57:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=06fc453ec13de75e156261e8fe4073334d0e00c2'/>
<id>urn:sha1:06fc453ec13de75e156261e8fe4073334d0e00c2</id>
<content type='text'>
Add SSE callbacks registration to PMU driver in order to disable
interrupt delegation for PMU interrupts. When interrupts are
undelegated send the PMU SSE event upon LCOFIP IRQ.

Signed-off-by: Clément Léger &lt;cleger@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
</feed>
