opensbi.git/lib/sbi/sbi_trap.c, branch v1.2

lib: sbi_trap: Add helper to get GVA in sbi_trap_regs

2022-09-13T11:12:59Z

The GVA bit is in mstatus on RV64, and in mstatush in RV32. Refactor code handling this in sbi_trap_handler into a helper function to extract GVA from sbi_trap_regs, so that future code accessing GVA can be XLEN-agnostic. Signed-off-by: Vivian Wang Reviewed-by: Andrew Jones Reviewed-by: Anup Patel

include: sbi: Reduce includes in sbi_pmu.h

2022-09-01T11:23:28Z

The sbi_pmu.h should only include minimal required headers whereas sbi_pmu.c should include all required headers. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Atish Patra

lib: sbi: Use the official extension name for AIA M-mode CSRs

2022-08-22T03:31:33Z

The arch review of AIA spec is completed and we now have official extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode AIA CSRs). Refer, section 1.6 of the latest AIA v0.3.1 stable specification at https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32/riscv-interrupts-032.pdf) Based on above, we update generic library to use "Smaia" extension name for AIA M-mode CSRs. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Atish Patra

lib: sbi_trap: Set hstatus.GVA when going to HS-mode

2022-08-22T03:20:23Z

The privileged spec specifies that on a trap to HS-mode, hstatus.GVA should be set to 1 if stval is written with a guest virtual address, and to 0 otherwise. Implement this by setting hstatus.GVA to trap->gva when redirecting traps to HS-mode. Signed-off-by: Vivian Wang Reviewed-by: Andrew Jones Reviewed-by: Anup Patel

lib: sbi_trap: Set hypervisor CSRs for HS-mode

2022-08-22T03:20:04Z

The hypervisor CSRs hstatus, htval, htinst should always be set if the trap is to be taken in HS-mode, regardless of which mode it came from. Signed-off-by: Vivian Wang Reviewed-by: Andrew Jones Reviewed-by: Anup Patel

lib: sbi: Set gva when creating sbi_trap_info

2022-08-22T03:19:49Z

In some cases the sbi_trap_info argument passed to sbi_trap_redirect is created from scratch by filling its fields. Since we previously added a gva field to struct sbi_trap_info, initialize gva in these cases also. Suggested-by: Andrew Jones Signed-off-by: Vivian Wang Reviewed-by: Andrew Jones Reviewed-by: Anup Patel

lib: sbi_trap: Redirect exception based on hedeleg

2022-06-13T05:32:49Z

HS-mode software can choose what exceptions to delegate to VS-mode using the hedeleg CSR. Synthetic VS/VU-mode exceptions should also honor hedeleg. They should be redirected to VS-mode if and only if delegated by HS-mode. Signed-off-by: dramforever Reviewed-by: Xiang W Reviewed-by: Anup Patel

lib: sbi: Convert hart features into hart extensions

2022-05-07T04:46:30Z

Since past few years, we have been using "hart features" in OpenSBI to represent all optionalities and multi-letter extensions defined by the RISC-V specifications. The RISC-V profiles specification has taken a different approach and started assigning extension names for all optionalities which did not have any extension name previously. (Refer, https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) Inspired from the RISC-V profiles specification, we convert OpenSBI hart features into hart extensions. Going forward, we align the extension naming with RISC-V profiles specification. Currently, only "time CSR" and "AIA CSR" have not been assigned extension name but for everything else we have a name. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: sbi: Add a simple external interrupt handling framework

2022-02-28T04:13:12Z

Currently, the external interrupt handling is scattered between sbi_init and sbi_trap. This patch moves all external interrupt handling into a simple framework called sbi_irqchip. Signed-off-by: Anup Patel Reviewed-by: Xiang W Reviewed-by: Atish Patra

lib: sbi: Add sbi_trap_set_external_irqfn() API

2022-02-15T15:03:55Z

This patch adds sbi_trap_set_external_irqfn() API which can be used by OpenSBI platform code to set a callback function for external interrupts. The RISC-V AIA IMSIC driver will use this API to implement inter-processor interrupts on-top-of MSIs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Atish Patra