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<title>opensbi.git/lib/sbi, branch v0.8</title>
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<id>http://cgit.235523.xyz/opensbi.git/atom/lib/sbi?h=v0.8</id>
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<updated>2020-06-20T05:06:13Z</updated>
<entry>
<title>lib: Don't return any invalid error from SBI ecall</title>
<updated>2020-06-20T05:06:13Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-06-10T13:09:53Z</published>
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<id>urn:sha1:2314101989684585f942b50a827aac4886825ba1</id>
<content type='text'>
We should only return valid error codes from SBI ecalls as
defined by the RISC-V SBI spec.

To achieve this:
1. We use SBI_Exxxx defines for OpenSBI internal errors with
   error values starting from -1000
2. We use SBI_ERR_xxxx defines for errors defined by SBI spec
3. We map some of the SBI_Exxxx defines to SBI_ERR_xxxx defines
   which are semantically same
4. We throw a error print and force return error code to
   SBI_ERR_FAILED in sbi_ecall_handler() if we see an invalid
   error code being returned to S-mode

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Fix 32/64 bits variable compatibility</title>
<updated>2020-06-20T03:17:11Z</updated>
<author>
<name>Liush</name>
<email>liush.damon@gmail.com</email>
</author>
<published>2020-06-19T03:55:19Z</published>
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<id>urn:sha1:9bd5f8f17d31f8989525643a04da87d090fe3033</id>
<content type='text'>
On RV64,"unsigned long" is 64bit and "unsigned int" is 32bit. So in
function "pmp_get" and "pmp_set", if "pmpcfg_shift &gt;= 32", "0xff &lt;&lt; pmpcfg_shift"
will go beyond "unsigned int" width. This patch tries to fix this issue.

In function 'pmp_get':
	cfgmask = (0xff &lt;&lt; pmpcfg_shift);
			--&gt;
	cfgmask = (0xffUL &lt;&lt; pmpcfg_shift);
In function 'pmp_set':
	cfgmask = ~(0xff &lt;&lt; pmpcfg_shift);
			--&gt;
	cfgmask = ~(0xffUL &lt;&lt; pmpcfg_shift);

Signed-off-by: Liush &lt;liush.damon@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: Fix the SBI_HART_HAS_MCOUNTEREN feature check</title>
<updated>2020-06-18T03:28:13Z</updated>
<author>
<name>Alistair Francis</name>
<email>alistair.francis@wdc.com</email>
</author>
<published>2020-06-17T00:07:33Z</published>
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<id>urn:sha1:637b348224d557cd27c187d4465a90852ddde8a9</id>
<content type='text'>
Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: Don't print delegation CSRs if there is no S-Mode</title>
<updated>2020-06-18T03:26:54Z</updated>
<author>
<name>Alistair Francis</name>
<email>alistair.francis@wdc.com</email>
</author>
<published>2020-06-17T00:06:15Z</published>
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<id>urn:sha1:d5725c24c6ea04368d90bc0f5af3ec20862b4a3b</id>
<content type='text'>
If the platform doesn't support S-Mode don't print the delegation
registers.

Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: Fix __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_vvma_asid_va()</title>
<updated>2020-06-15T03:54:27Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-06-06T12:03:48Z</published>
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<id>urn:sha1:e2c3f01af4329aa7e9009edee13b7cfdf379071f</id>
<content type='text'>
The arguments/parameters of __sbi_hfence_gvma_vmid_gpa() and
__sbi_hfence_vvma_asid_va() functions are swapped so we fix it.

Currently, we did not face any issues because QEMU does a full
TLB flush for all HFENCE instructions.

We also improve documentation of HFENCE.GVMA and HFENCE.VVMA
instruction encoding.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: Add RISC-V hypervisor v0.6.1 support</title>
<updated>2020-06-08T10:11:23Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-05-28T03:07:42Z</published>
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<id>urn:sha1:1b8c0128f1d79d69ea0a46b758fef4be8dc0a73e</id>
<content type='text'>
To support RISC-V hypervisor v0.6.1, we:
1. Don't need to explicitly forward WFI traps from VS/VU-mode
2. Have to delegate virtual instruction trap to HS-mode
3. Have to update trap redirection for changes in HSTATUS CSR

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi_hart: Detect number of supported PMP regions</title>
<updated>2020-05-19T03:49:48Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-05-18T06:34:18Z</published>
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<id>urn:sha1:a38bea9341a2da29bec00d5253ac71da8ca06bab</id>
<content type='text'>
It is not mandatory for a RISC-V systems to implement all PMP
regions so we have to check all PMPADDRx CSRs to determine excat
number of supported PMP regions.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Few cosmetic improvements to HART feature detection</title>
<updated>2020-05-19T03:49:44Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-05-11T06:12:54Z</published>
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<id>urn:sha1:2966510eedf03e47e13f3e1a88039bd4199c1085</id>
<content type='text'>
This patch does few cosmetic improvements to HART feature detection:
1. Remove sbi_ perfix from HART feature detection functions
   because all local/static functions in sbi_hart.c don't have
   sbi_ prefix
2. Remove sbi_hart_set_feature() because it's quite small and
   local/static in sbi_hart.c

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>include: sbi: Use scratch pointer as parmeter in HART feature APIs</title>
<updated>2020-05-19T03:49:42Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-05-11T06:00:15Z</published>
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<id>urn:sha1:63b0f5f71a4d6bf8539a8cbfa27228dc76e7d71a</id>
<content type='text'>
It makes more sense to have scratch pointer as parameter in
HART feature APIs because:
1. We already have scratch pointer at places where these APIs
   are used.
2. This is consistent with lot of other APIs in sbi_hart.h

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Print platform HART count just before boot HART id</title>
<updated>2020-05-19T03:49:39Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-05-10T06:19:59Z</published>
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<id>urn:sha1:3a8fc8135714e39bef99cbf2a4b31e6f2f19a929</id>
<content type='text'>
On platforms with continuous HART ids starting from zero:
0 &lt;= boot HART id &lt; platform HART count

The above co-relation of boot HART id and platform HART count
is true for most RISC-V platfors so it's better to print platform
HART count just before boot HART id.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
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