opensbi.git/lib/utils/cache/fdt_sifive_ccache.c, branch master Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/opensbi.git/atom/lib/utils/cache/fdt_sifive_ccache.c?h=master 2025-10-28T05:57:51Z utils: cache: Add SiFive ccache controller 2025-10-28T05:57:51Z Vincent Chen vincent.chen@sifive.com 2025-10-20T06:34:05Z urn:sha1:8ea972838cf3f398b1a2896e645c8c2fb23e2159 SiFive Composable cache is a L3 share cache of the core complex. Add this driver to support the share cache maintenance operations via the MMIO registers. Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Nick Hu <nick.hu@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-3-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>