opensbi.git/lib/utils/cache, branch release-1.8.x

lib: utils/cache: Add SiFive Extensible Cache (EC) driver

2025-12-08T04:31:20Z

Add support for SiFive Extensible Cache (EC) controller with multi-slice architecture. The driver implements cache maintenance operations through MMIO register interface. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Samuel Holland Signed-off-by: Samuel Holland Co-developed-by: Yong-Xuan Wang Signed-off-by: Yong-Xuan Wang Signed-off-by: Nick Hu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-3-8423a721924c@sifive.com Signed-off-by: Anup Patel

lib: utils/cache: Add SiFive PL2 controller

2025-12-08T04:31:05Z

SiFive Private L2(PL2) cache is a private cache owned by each hart. Add this driver to support private cache flush operations via the MMIO registers. Co-developed-by: Eric Lin Signed-off-by: Eric Lin Co-developed-by: Zong Li Signed-off-by: Zong Li Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Samuel Holland Signed-off-by: Samuel Holland Signed-off-by: Nick Hu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-2-8423a721924c@sifive.com Signed-off-by: Anup Patel

lib: utils/cache: Handle last-level cache correctly in fdt_cache_add()

2025-12-08T04:21:53Z

The fdt_cache_add() helper attempts to retrieve the next-level cache and returns SBI_ENOENT when there is none. Since this condition only indicates that the current cache is the last-level cache, the helper should not treat it as an error. Signed-off-by: Nick Hu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-1-8423a721924c@sifive.com Signed-off-by: Anup Patel

lib: utils/cache: Add fdt cmo helpers

2025-10-28T05:57:53Z

Add the helpers to build up the cache hierarchy via FDT and provide some cmo functions for the user who want to flush the entire cache. Signed-off-by: Nick Hu Reviewed-by: Samuel Holland Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-4-69a132447d8a@sifive.com Signed-off-by: Anup Patel

utils: cache: Add SiFive ccache controller

2025-10-28T05:57:51Z

SiFive Composable cache is a L3 share cache of the core complex. Add this driver to support the share cache maintenance operations via the MMIO registers. Co-developed-by: Samuel Holland Signed-off-by: Samuel Holland Signed-off-by: Vincent Chen Co-developed-by: Nick Hu Signed-off-by: Nick Hu Reviewed-by: Samuel Holland Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-3-69a132447d8a@sifive.com Signed-off-by: Anup Patel

lib: utils: Add FDT cache library

2025-10-28T05:57:10Z

Add the FDT cache library so we can build up the cache topology via the 'next-level-cache' DT property. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Andy Chiu Signed-off-by: Andy Chiu Signed-off-by: Nick Hu Reviewed-by: Samuel Holland Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-2-69a132447d8a@sifive.com Signed-off-by: Anup Patel

lib: utils: Add cache flush library

2025-10-28T05:09:59Z

The current RISC-V CMO only defines how to flush a cache block. However, certain use cases, such as power management, may require flushing the entire cache. Therefore, a framework is being introduced to allow vendors to flush the entire cache using their own methods. Signed-off-by: Nick Hu Reviewed-by: Samuel Holland Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-1-69a132447d8a@sifive.com Signed-off-by: Anup Patel