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<title>opensbi.git/lib/utils/fdt, branch v1.1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/lib/utils/fdt?h=v1.1</id>
<link rel='self' href='http://cgit.235523.xyz/opensbi.git/atom/lib/utils/fdt?h=v1.1'/>
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<updated>2022-05-14T04:48:12Z</updated>
<entry>
<title>lib: utils/fdt: rename fdt_parse_max_hart_id</title>
<updated>2022-05-14T04:48:12Z</updated>
<author>
<name>Jan Remes</name>
<email>jan.remes@codasip.com</email>
</author>
<published>2022-05-13T10:58:43Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=1bc67db80cb0a10d8ebbaaf550a79eee2a07158e'/>
<id>urn:sha1:1bc67db80cb0a10d8ebbaaf550a79eee2a07158e</id>
<content type='text'>
The function returns the highest hart-id of the harts actually used in
the system (enabled). Change the name to reflect this fact.

Signed-off-by: Jan Remes &lt;jan.remes@codasip.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: check if CPU node is enabled</title>
<updated>2022-05-14T04:46:50Z</updated>
<author>
<name>Jan Remes</name>
<email>jan.remes@codasip.com</email>
</author>
<published>2022-05-13T10:58:41Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=616da52e186dfecb767ee7bd5913ef70028a422d'/>
<id>urn:sha1:616da52e186dfecb767ee7bd5913ef70028a422d</id>
<content type='text'>
Ignore CPU nodes in FDT that are not enabled.

Signed-off-by: Jan Remes &lt;jan.remes@codasip.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/fdt: introduce fdt_node_is_enabled()</title>
<updated>2022-05-14T04:46:24Z</updated>
<author>
<name>Jan Remes</name>
<email>jan.remes@codasip.com</email>
</author>
<published>2022-05-13T10:58:40Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=90a9dd2b22bb5441df85a23e4e4690bec14fa1e5'/>
<id>urn:sha1:90a9dd2b22bb5441df85a23e4e4690bec14fa1e5</id>
<content type='text'>
If an FDT node contains a "status" property and this property is not
"ok" or "okay", this node should be ignored. Introduce a function that
checks this.

Signed-off-by: Jan Remes &lt;jan.remes@codasip.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Convert hart features into hart extensions</title>
<updated>2022-05-07T04:46:30Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-04-28T15:59:22Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=cad6c91045331009f38d13f63956a119b0b053c8'/>
<id>urn:sha1:cad6c91045331009f38d13f63956a119b0b053c8</id>
<content type='text'>
Since past few years, we have been using "hart features" in OpenSBI
to represent all optionalities and multi-letter extensions defined
by the RISC-V specifications.

The RISC-V profiles specification has taken a different approach and
started assigning extension names for all optionalities which did not
have any extension name previously.
(Refer, https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc)

Inspired from the RISC-V profiles specification, we convert OpenSBI
hart features into hart extensions. Going forward, we align the
extension naming with RISC-V profiles specification. Currently, only
"time CSR" and "AIA CSR" have not been assigned extension name but
for everything else we have a name.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: support 'reg-offset' property</title>
<updated>2022-04-17T08:27:48Z</updated>
<author>
<name>Zong Li</name>
<email>zong.li@sifive.com</email>
</author>
<published>2022-04-15T02:24:20Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=5c5cbb53a4fd2f7d2a7038b584f8ee01266cef04'/>
<id>urn:sha1:5c5cbb53a4fd2f7d2a7038b584f8ee01266cef04</id>
<content type='text'>
reg-offset property is used for offset to apply to the mapbase
from the start of the registers in 8250 UART. In Linux kernel,
it has been handled in 8250 UART driver.

dt-bindings:
&lt;linux&gt;/Documentation/devicetree/bindings/serial/8250.yaml

Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: serial: Initial commit of xlnx-uartlite</title>
<updated>2022-02-28T04:20:09Z</updated>
<author>
<name>Alistair Francis</name>
<email>alistair.francis@wdc.com</email>
</author>
<published>2022-02-24T05:01:46Z</published>
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<id>urn:sha1:4998a712b2ab504eff306110879ee05af6050177</id>
<content type='text'>
Initial commit of the xlnx-uartlite device and FDT support. This was
tested by running OpenSBI on a modified QEMU virt machine using the
xlnx-uartlite for serial.

Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: Disable appropriate APLIC DT nodes in fdt_fixups()</title>
<updated>2022-02-15T15:09:15Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2021-06-15T06:07:59Z</published>
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<id>urn:sha1:8e2ef4f7af5affebc8464dd9c4b98501df14e23e</id>
<content type='text'>
We should disable APLIC DT nodes in fdt_fixups() which are not
accessible to the next booting stage based on currently assigned
domain.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Add FDT based driver for APLIC</title>
<updated>2022-02-15T15:09:01Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2021-04-08T12:40:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=34612193af92f29446a3d59bc4f983c9cfe4b989'/>
<id>urn:sha1:34612193af92f29446a3d59bc4f983c9cfe4b989</id>
<content type='text'>
We add simple FDT irqchip driver for APLIC so that generic platform (and
other FDT based platforms) can utilize common APLIC initialization library.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils: Disable appropriate IMSIC DT nodes in fdt_fixups()</title>
<updated>2022-02-15T15:07:27Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2021-06-15T05:49:40Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=7127aaaaf709c0a5a08b70e993a135b27eb50006'/>
<id>urn:sha1:7127aaaaf709c0a5a08b70e993a135b27eb50006</id>
<content type='text'>
We should disable IMSIC DT nodes in fdt_fixups() which are not
accessible to the next booting stage based on currently assigned
domain.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Add FDT based driver for IMSIC</title>
<updated>2022-02-15T15:07:05Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2021-04-21T09:57:29Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=811da5c54180aafde6cb7740b1ccaf92d1017f24'/>
<id>urn:sha1:811da5c54180aafde6cb7740b1ccaf92d1017f24</id>
<content type='text'>
We add simple FDT irqchip driver for IMSIC so that generic platform
(and other FDT based platforms) can utilize common IMIC library.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
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