opensbi.git/lib/utils/hsm/Kconfig, branch masterUnnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/opensbi.git/atom/lib/utils/hsm/Kconfig?h=master2026-02-11T06:33:50Zlib: utils/hsm: factor out ATCSMU code into an HSM driver2026-02-11T06:33:50ZBen Zong-You Xieben717@andestech.com2025-12-29T07:19:10Zurn:sha1:9ffacc8ae1ca07ed36d57f887d62a65ae7a44223
Refactor ATCSMU (System Management Unit) support by moving it from a
system utility into a dedicated FDT-based HSM driver.
Key changes include:
- Moving the functions in lib/utils/sys/atcsmu.c into the new HSM driver
- Moving hart start and stop operations on AE350 platform into the new
HSM driver
- Converting the assembly-based functions in sleep.S to C code for the
readability
- Updating the ATCWDT200 driver
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Link: https://lore.kernel.org/r/20251229071914.1451587-2-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org>
lib: utils/hsm: Add SiFive TMC0 driver2025-10-28T05:58:03ZNick Hunick.hu@sifive.com2025-10-20T06:34:11Zurn:sha1:1514a327306b8e6bca7194676ba810543f88938d
The SiFive TMC0 controls the tile power domains on SiFive platform. The
CPU enters the low power state via the `CEASE` instruction after
configuring the TMC0. Any devices that inside the tile power domain will
be power gated, including the private cache. Therefore flushing the
private cache before entering the low power state.
Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Cyan Yang <cyan.yang@sifive.com>
Signed-off-by: Nick Hu <nick.hu@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org>
platform: spacemit: Add HSM driver2025-10-20T04:59:50ZXianbin Zhuxianbin.zhu@linux.spacemit.com2025-09-25T09:48:56Zurn:sha1:fb70fe8b98c0e6ca23201bf7014ae85a3ef692b9
Add code to bring up all 8 cores during OpenSBI initialization so
that the Linux kernel can detect and use all cores properly.
Co-authored-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Signed-off-by: Xianbin Zhu <xianbin.zhu@linux.spacemit.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-2-0885a8a70f8e@linux.spacemit.com
Signed-off-by: Anup Patel <anup@brainfault.org>
lib: utils/hsm: Add RPMI HSM driver2024-12-06T03:56:43ZSubrahmanya Lingappaslingappa@ventanamicro.com2024-08-06T05:25:01Zurn:sha1:33ee9b8240fee298ddd357a68096652286024670
The RPMI HSM service group provides set of routine to query and control
power states of a Hart. Add RPMI based Hart State Management (HSM) driver.
Signed-off-by: Subrahmanya Lingappa <slingappa@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
lib: utils: Add simple FDT based HSM driver framework2024-12-06T03:56:40ZAnup Patelapatel@ventanamicro.com2024-08-06T05:15:11Zurn:sha1:ff4769bf08b50c61bb48f37ea00a17737096e2b5
The generic platform can have multiple HSM drivers so add a simple
FDT based HSM driver framework.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>