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<title>opensbi.git/lib/utils/hsm/objects.mk, branch master</title>
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<updated>2026-02-11T06:33:50Z</updated>
<entry>
<title>lib: utils/hsm: factor out ATCSMU code into an HSM driver</title>
<updated>2026-02-11T06:33:50Z</updated>
<author>
<name>Ben Zong-You Xie</name>
<email>ben717@andestech.com</email>
</author>
<published>2025-12-29T07:19:10Z</published>
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<id>urn:sha1:9ffacc8ae1ca07ed36d57f887d62a65ae7a44223</id>
<content type='text'>
Refactor ATCSMU (System Management Unit) support by moving it from a
system utility into a dedicated FDT-based HSM driver.

Key changes include:

- Moving the functions in lib/utils/sys/atcsmu.c into the new HSM driver
- Moving hart start and stop operations on AE350 platform into the new
  HSM driver
- Converting the assembly-based functions in sleep.S to C code for the
  readability
- Updating the ATCWDT200 driver

Signed-off-by: Ben Zong-You Xie &lt;ben717@andestech.com&gt;
Signed-off-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Link: https://lore.kernel.org/r/20251229071914.1451587-2-ben717@andestech.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/hsm: Add SiFive TMC0 driver</title>
<updated>2025-10-28T05:58:03Z</updated>
<author>
<name>Nick Hu</name>
<email>nick.hu@sifive.com</email>
</author>
<published>2025-10-20T06:34:11Z</published>
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<id>urn:sha1:1514a327306b8e6bca7194676ba810543f88938d</id>
<content type='text'>
The SiFive TMC0 controls the tile power domains on SiFive platform. The
CPU enters the low power state via the `CEASE` instruction after
configuring the TMC0. Any devices that inside the tile power domain will
be power gated, including the private cache. Therefore flushing the
private cache before entering the low power state.

Co-developed-by: Vincent Chen &lt;vincent.chen@sifive.com&gt;
Signed-off-by: Vincent Chen &lt;vincent.chen@sifive.com&gt;
Reviewed-by: Cyan Yang &lt;cyan.yang@sifive.com&gt;
Signed-off-by: Nick Hu &lt;nick.hu@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: spacemit: Add HSM driver</title>
<updated>2025-10-20T04:59:50Z</updated>
<author>
<name>Xianbin Zhu</name>
<email>xianbin.zhu@linux.spacemit.com</email>
</author>
<published>2025-09-25T09:48:56Z</published>
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<id>urn:sha1:fb70fe8b98c0e6ca23201bf7014ae85a3ef692b9</id>
<content type='text'>
Add code to bring up all 8 cores during OpenSBI initialization so
that the Linux kernel can detect and use all cores properly.

Co-authored-by: Troy Mitchell &lt;troy.mitchell@linux.spacemit.com&gt;
Signed-off-by: Troy Mitchell &lt;troy.mitchell@linux.spacemit.com&gt;
Signed-off-by: Xianbin Zhu &lt;xianbin.zhu@linux.spacemit.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-2-0885a8a70f8e@linux.spacemit.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: Initialize miscellaneous drivers in one pass</title>
<updated>2025-02-12T16:09:25Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2025-01-19T19:03:57Z</published>
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<id>urn:sha1:434add551c2a17cac3804ff0f587d31be03f070e</id>
<content type='text'>
For driver subsystems that are not tightly integrated into the OpenSBI
init sequence, it is not important that the drivers are initialized in
any particular order. By putting all of these drivers in one array, they
can all be initialized with a single pass through the devicetree. This
saves about 10 ms of boot time on HiFive Unmatched.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/hsm: Add RPMI HSM driver</title>
<updated>2024-12-06T03:56:43Z</updated>
<author>
<name>Subrahmanya Lingappa</name>
<email>slingappa@ventanamicro.com</email>
</author>
<published>2024-08-06T05:25:01Z</published>
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<id>urn:sha1:33ee9b8240fee298ddd357a68096652286024670</id>
<content type='text'>
The RPMI HSM service group provides set of routine to query and control
power states of a Hart. Add RPMI based Hart State Management (HSM) driver.

Signed-off-by: Subrahmanya Lingappa &lt;slingappa@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils: Add simple FDT based HSM driver framework</title>
<updated>2024-12-06T03:56:40Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2024-08-06T05:15:11Z</published>
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<id>urn:sha1:ff4769bf08b50c61bb48f37ea00a17737096e2b5</id>
<content type='text'>
The generic platform can have multiple HSM drivers so add a simple
FDT based HSM driver framework.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
</content>
</entry>
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