opensbi.git/lib/utils/hsm, branch master

lib: utils/suspend: add Andes ATCSMU suspend driver

2026-02-11T06:44:04Z

Implement a system-wide suspend driver for the Andes AE350 platform. This driver supports Andes-specific deep sleep (suspend to RAM) and light sleep (suspend to standby) functionalities via the ATCSMU. The major differences between deep sleep and light sleep are: - Power Domain and Resume Path: Deep sleep powers down the core domain. Consequently, harts waking from deep sleep resume from the reset vector. Light sleep utilizes clock gating to the core domain; harts maintain state and resume execution at the instruction immediately following the WFI instruction. - Primary Hart Wakeup: In both modes, the primary hart is woken by UART or RTC alarm interrupts. In deep sleep, the primary hart is additionally responsible for re-enabling the Last Level Cache (LLC) and restoring Andes-specific CSRs. - Secondary Hart Wakeup: In light sleep, secondary harts are woken by an IPI sent from the primary hart. In deep sleep, they are woken by an ATCSMU hardware wake-up command. Furthermore, secondary harts must restore Andes-specific CSRs when returning from deep sleep. Signed-off-by: Ben Zong-You Xie Signed-off-by: Leo Yu-Chi Liang Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com Signed-off-by: Anup Patel

lib: utils/cache: add Andes last level cache controller

2026-02-11T06:43:01Z

Introduce a FDT-based driver for the Andes Last Level Cache (LLC) controller to support cache maintenance operations. Signed-off-by: Ben Zong-You Xie Link: https://lore.kernel.org/r/20251229071914.1451587-5-ben717@andestech.com Signed-off-by: Anup Patel

platform: generic/andes: add CSR save and restore functions for AE350 platform

2026-02-11T06:34:01Z

Implement a save and restore mechanism for Andes-specific CSRs to support hardware power-saving modes, such as CPU hotplug or suspend to RAM. Signed-off-by: Ben Zong-You Xie Signed-off-by: Leo Yu-Chi Liang Link: https://lore.kernel.org/r/20251229071914.1451587-3-ben717@andestech.com Signed-off-by: Anup Patel

lib: utils/hsm: factor out ATCSMU code into an HSM driver

2026-02-11T06:33:50Z

Refactor ATCSMU (System Management Unit) support by moving it from a system utility into a dedicated FDT-based HSM driver. Key changes include: - Moving the functions in lib/utils/sys/atcsmu.c into the new HSM driver - Moving hart start and stop operations on AE350 platform into the new HSM driver - Converting the assembly-based functions in sleep.S to C code for the readability - Updating the ATCWDT200 driver Signed-off-by: Ben Zong-You Xie Signed-off-by: Leo Yu-Chi Liang Link: https://lore.kernel.org/r/20251229071914.1451587-2-ben717@andestech.com Signed-off-by: Anup Patel

lib: utils/suspend: Add SiFive SMC0 driver

2025-10-28T05:58:10Z

The SiFive SMC0 controls the clock and power domain of the core complex on the SiFive platform. The core complex enters the low power state after the secondary cores enter the tile power gating and last core execute the `CEASE` instruction with the corresponding SMC0 configurations. The devices that inside both tile power domain and core complex power domain will be off, including caches and timer. Therefore we need to flush the last level cache before entering the core complex power gating and update the timer after waking up. Reviewed-by: Cyan Yang Reviewed-by: Anup Patel Signed-off-by: Nick Hu Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-12-69a132447d8a@sifive.com Signed-off-by: Anup Patel

lib: utils/hsm: Add SiFive TMC0 driver

2025-10-28T05:58:03Z

The SiFive TMC0 controls the tile power domains on SiFive platform. The CPU enters the low power state via the `CEASE` instruction after configuring the TMC0. Any devices that inside the tile power domain will be power gated, including the private cache. Therefore flushing the private cache before entering the low power state. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Reviewed-by: Cyan Yang Signed-off-by: Nick Hu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com Signed-off-by: Anup Patel

platform: spacemit: Add HSM driver

2025-10-20T04:59:50Z

Add code to bring up all 8 cores during OpenSBI initialization so that the Linux kernel can detect and use all cores properly. Co-authored-by: Troy Mitchell Signed-off-by: Troy Mitchell Signed-off-by: Xianbin Zhu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-2-0885a8a70f8e@linux.spacemit.com Signed-off-by: Anup Patel

lib: rpmi: Make RPMI drivers as non-experimental

2025-06-24T03:12:27Z

As RPMI v1.0 specification is frozen, disable the experimental tag for such RPMI drivers. Signed-off-by: Rahul Pathak Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250618053854.2577299-2-rpathak@ventanamicro.com Signed-off-by: Anup Patel

lib: utils: hsm: Do not fail on EALREADY in rpmi-hsm fixup.

2025-06-14T05:01:32Z

In case harts are divided into groups that use different rpmi-hsm channels in different mailboxes, the suspend state fixup function will return EALREADY on secondary entry, simply skip on this error. Reviewed-by: Anup Patel Signed-off-by: Ziang Wang Link: https://lore.kernel.org/r/20250507074620.3162747-1-wangziang.ok@bytedance.com Signed-off-by: Anup Patel

lib: utils: Constify FDT driver definitions

2025-02-19T12:17:24Z

The carray referencing these definitions assumes they are const. Fixes: 6a26726e08e4 ("lib/utils: reset: Add RPMI System Reset driver") Fixes: 13f55f33a1d3 ("lib: utils/suspend: Add RPMI system suspend driver") Fixes: 33ee9b8240fe ("lib: utils/hsm: Add RPMI HSM driver") Fixes: 591a98bdd549 ("lib: utils/cppc: Add RPMI CPPC driver") Signed-off-by: Samuel Holland Reviewed-by: Anup Patel