opensbi.git/lib/utils/ipi/andes_plicsw.c, branch v1.4

lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme

2023-12-06T11:53:27Z

The old scheme doesn't allow sending hart0 self-IPI as the corresponding bit on pending register is hardwired to 0, this could lead to unhandle IPIs on SMP systems, esp. on single-core. Furthermore, the limitation of old scheme is 8-core, instead of reserving source hart information, we assign bit (x + 1) as the enable and pending bit of hartx, this also expands the bootable hart number. The following diagram shows the enable bits of the new scheme on 32-core Andes platform. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> To send IPI to hart0, for example, another hart (including hart0 itself) will set bit 1 of first word on the pending register. We also fix indentation in andes_plicsw.h along with this patch. Fixes: ce7c490719ed ("lib: utils/ipi: Add Andes fdt ipi driver support") Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin Reviewed-by: Randolph Reported-by: Lad Prabhakar Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005665.html Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar Reviewed-by: Anup Patel

lib: utils: timer/ipi: Update memregion flags for PLMT and PLICSW

2023-10-06T11:23:26Z

This patch adds unspecified permission flags for the PLICSW region and updates the permission of the PLMT region. With this update, both regions will become M-mode only read/write regions in the root domain. Domain0 Region00: 0x00000000f0300000-0x00000000f0300fff M: (I,R,W) S/U: (R,W) Domain0 Region01: 0x0000000000040000-0x000000000005ffff M: (R,W) S/U: () Domain0 Region02: 0x0000000000000000-0x000000000003ffff M: (R,X) S/U: () > Domain0 Region03: 0x00000000e6000000-0x00000000e60fffff M: (I,R,W) S/U: () > Domain0 Region04: 0x00000000e6400000-0x00000000e67fffff M: (I,R,W) S/U: () Domain0 Region05: 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) The PMP rules of AE350-AX65 (single-core) w/ Smepmp: p/x $pmpcfg0 $1 = {0x1f9b9b9d9b1e00, pmp0cfg = {0x0}, L--AAXWR pmp1cfg = {0x1e} (00011110), pmpaddr1: 0xf0300000 ~ 0xf0300fff (UART1) pmp2cfg = {0x9b} (10011011), pmpaddr2: 0x40000 ~ 0x5ffff pmp3cfg = {0x9d} (10011101), pmpaddr3: 0x0 ~ 0x3ffff pmp4cfg = {0x9b} (10011011), pmpaddr4: 0xe6000000 ~ 0xe60fffff (PLMT) pmp5cfg = {0x9b} (10011011), pmpaddr5: 0xe6400000 ~ 0xe67fffff (PLICSW) pmp6cfg = {0x1f} (00011111), pmpaddr6: 0x0 ~ 0xffffffffff pmp7cfg = {0x0 }} The PMP rules of AE350-AX45MP (qual-core) w/o Smepmp: p/x $pmpcfg0 $1 = {0x1f181818181b, L--AAXWR pmp0cfg = {0x1b}, (00011011), pmpaddr0: 0xf0300000 ~ 0xf0300fff (UART1) pmp1cfg = {0x18}, (00011000), pmpaddr1: 0x40000 ~ 0x5ffff pmp2cfg = {0x18}, (00011000), pmpaddr2: 0x0 ~ 0x3ffff pmp3cfg = {0x18}, (00011000), pmpaddr3: 0xe6000000 ~ 0xe60fffff (PLMT) pmp4cfg = {0x18}, (00011000), pmpaddr4: 0xe6400000 ~ 0xe67fffff (PLICSW) pmp5cfg = {0x1f}, (00011111), pmpaddr5: 0x0 ~ 0x1ffffffff pmp6cfg = {0x0 }} Note that starting from this patch, we restrict the S/U-mode read permission to the PLMT region, since we should read the TIME CSR in a lower privilege mode. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

lib: sbi: Prefer hartindex over hartid in IPI framework

2023-09-24T06:09:38Z

Let us prefer hartindex over hartid in IPI framework which in-turn forces IPI users to also prefer hartindex. Signed-off-by: Anup Patel

lib: utils/ipi: Add Andes fdt ipi driver support

2022-10-23T05:01:01Z

Move Andes PLICSW ipi device to fdt ipi framework, this patch is based on Leo's modified IPI scheme on PLICSW. Current IPI scheme uses bit 0 of pending reigster on PLICSW to send IPI from hart 0 to hart 7, but bit 0 needs to be hardwired to 0 according to spec. After some investigation, self-IPI seems to be seldom or never used, so we re-order the IPI scheme to support 8 core platforms. dts example (Quad-core AX45MP): plicsw: interrupt-controller@e6400000 { compatible = "andestech,plicsw"; reg = <0x00000000 0xe6400000 0x00000000 0x00400000>; interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3 &CPU2_intc 3 &CPU3_intc 3>; interrupt-controller; #address-cells = <2>; #interrupt-cells = <2>; }; Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel