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<title>opensbi.git/lib/utils/ipi, branch v1.2</title>
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<id>http://cgit.235523.xyz/opensbi.git/atom/lib/utils/ipi?h=v1.2</id>
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<updated>2022-12-17T05:31:00Z</updated>
<entry>
<title>lib: utils/ipi: mswi: add T-Head C9xx CLINT compatible</title>
<updated>2022-12-17T05:31:00Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>uwu@icenowy.me</email>
</author>
<published>2022-12-12T08:22:36Z</published>
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<id>urn:sha1:a8ee82cd8c008f09c91b5c307de4c9b37660ff71</id>
<content type='text'>
Althoug the MTIMER part of a C9xx CLINT differs from a SiFive one, the
MSWI part is compliant.

Add T-Head C9xx CLINT compatible string to fdt_ipi_mswi code, sharing
the same codepath with SiFive CLINT.

Signed-off-by: Icenowy Zheng &lt;uwu@icenowy.me&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/ipi: Add Andes fdt ipi driver support</title>
<updated>2022-10-23T05:01:01Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2022-10-14T00:32:50Z</published>
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<id>urn:sha1:ce7c490719ed4e268979c8b6b54a5252396fbb3b</id>
<content type='text'>
Move Andes PLICSW ipi device to fdt ipi framework, this patch is based
on Leo's modified IPI scheme on PLICSW.

Current IPI scheme uses bit 0 of pending reigster on PLICSW to send IPI
from hart 0 to hart 7, but bit 0 needs to be hardwired to 0 according
to spec. After some investigation, self-IPI seems to be seldom or never
used, so we re-order the IPI scheme to support 8 core platforms.

dts example (Quad-core AX45MP):

  plicsw: interrupt-controller@e6400000 {
          compatible = "andestech,plicsw";
          reg = &lt;0x00000000 0xe6400000 0x00000000 0x00400000&gt;;
          interrupts-extended = &lt;&amp;CPU0_intc 3
                                 &amp;CPU1_intc 3
                                 &amp;CPU2_intc 3
                                 &amp;CPU3_intc 3&gt;;
          interrupt-controller;
          #address-cells = &lt;2&gt;;
          #interrupt-cells = &lt;2&gt;;
  };

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/fdt: Use kconfig for enabling/disabling</title>
<updated>2022-08-08T04:04:08Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-08-08T04:04:08Z</published>
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<id>urn:sha1:68d7b85ec75119787d7c672062de5d29156c44be</id>
<content type='text'>
We update FDT support makefile to use kconfig for enabling/disabling.
To avoid compilation errors, we also enable FDT for each platform.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Acked-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Tested-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/ipi: Use kconfig for enabling/disabling drivers</title>
<updated>2022-08-08T04:03:45Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-08-08T04:03:45Z</published>
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<id>urn:sha1:76af9d40da21c4c67efb7730de263f914452fca0</id>
<content type='text'>
We update ipi drivers makefile to use kconfig for enabling/disabling
drivers. To avoid compile errors, we also enable appropriate ipi
drivers for each platform.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Acked-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Tested-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Remove Allwinner D1 CLINT compatibles</title>
<updated>2022-06-22T05:25:37Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2022-06-22T04:57:42Z</published>
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<id>urn:sha1:6f1fe98c2f565a394f258178b0daa3843672395c</id>
<content type='text'>
The allwinner,sun20i-d1-clint compatible string is not documented in any
official binding, so it should not be used by drivers.

The MSWI in the D1 CLINT is compatible with the ACLINT specification, so
it can take advantage of generic driver support. However, that is only
possible if the MSWI and MTIMER are split into separate DT nodes. This
means the final binding for this device is likely to be incompatible
with what is implemented here.

Remove this compatible string from the driver to prevent it from
appearing in a stable version and causing future issues.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Add a separate compatible for the D1 CLINT</title>
<updated>2022-06-21T03:50:59Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2021-10-20T01:58:38Z</published>
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<id>urn:sha1:7738345396fbbae543a5af14fbc965d9163c12a0</id>
<content type='text'>
The CLINT in the Allwinner D1 SoC apparently does not support 64-bit
MMIO access. A property was added to support this quirk (and that
property was copied to the ACLINT MTIMER code). However, since this
difference in behavior makes the D1 CLINT incompatible with the SiFive
CLINT's programming interface, a better solution is to use a separate
compatible string.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/fdt: Require match data to be const</title>
<updated>2022-05-30T05:02:35Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2022-05-29T18:32:11Z</published>
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<id>urn:sha1:fab0379bb60d6e177018b53f07718b69ba34948d</id>
<content type='text'>
Match data stores hardware attributes which do not change at runtime, so
it does not need to be mutable. Make it const.

Reviewed-by: Guo Ren &lt;guoren@kernel.org&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/ipi: Generate FDT ipi driver list at compile-time</title>
<updated>2022-05-13T03:56:35Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-05-13T03:56:35Z</published>
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<id>urn:sha1:4ee0c579699ae2a083edd7033a27044763c10a81</id>
<content type='text'>
Instead of having FDT ipi driver list hard-coded in the C source,
we generate it using carray.sh at compile-time.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/ipi: Fix size check in aclint_mswi_cold_init()</title>
<updated>2022-01-11T12:47:07Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-01-06T03:32:45Z</published>
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<id>urn:sha1:5b9960379fae14b554c953b0d4139f4b1a57cd5e</id>
<content type='text'>
Currently, the ACLINT MSWI size check is forcing size to be at least
0x4000. This is inappropriate check because most systems will never
utilize full 16KB for a single ACLINT MSWI device so instead we should
check that ACLINT MSWI size is enough for on the associated HARTs.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Dong Du &lt;Dd_nirvana@sjtu.edu.cn&gt;
Reviewed-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
</content>
</entry>
<entry>
<title>include: sbi_utils: Introduce an helper to get fdt base address</title>
<updated>2021-11-02T05:53:16Z</updated>
<author>
<name>Alexandre Ghiti</name>
<email>alexandre.ghiti@canonical.com</email>
</author>
<published>2021-10-27T07:43:36Z</published>
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<id>urn:sha1:c891acca172dfc60719419e19338508a83d97931</id>
<content type='text'>
This simply adds an helper to get fdt address which is more explicit than
sbi_scratch_thishart_arg1_ptr.

Signed-off-by: Alexandre Ghiti &lt;alexandre.ghiti@canonical.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
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