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<title>opensbi.git/lib/utils/ipi, branch v1.3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/lib/utils/ipi?h=v1.3</id>
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<updated>2023-06-05T10:32:59Z</updated>
<entry>
<title>lib: utils/ipi: Use scratch space to save per-HART MSWI pointer</title>
<updated>2023-06-05T10:32:59Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-04-19T15:53:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=acbd8fce9e5d92f07d344388a3b046f1722ce072'/>
<id>urn:sha1:acbd8fce9e5d92f07d344388a3b046f1722ce072</id>
<content type='text'>
Instead of using a global array indexed by hartid, we should use
scratch space to save per-HART MSWI pointer.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/ipi: Use heap in ACLINT MSWI driver</title>
<updated>2023-06-05T10:25:56Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-04-19T11:24:13Z</published>
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<id>urn:sha1:5a8cfcdf19d98b8dc5dd5a087a2eceb7f5b185fb</id>
<content type='text'>
Let's use heap allocation in ACLINT MSWI driver instead of using
a fixed size global array.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/ipi: buffer overrun aclint_mswi_cold_init</title>
<updated>2023-06-04T09:43:50Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2023-05-29T09:27:20Z</published>
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<id>urn:sha1:df75e0995689842b3022a4a8d4d69e980430c129</id>
<content type='text'>
The parameter checks in aclint_mswi_cold_init() don't guard against a
buffer overrun.

mswi_hartid2data is defined as an array of SBI_HARTMASK_MAX_BITS entries.
The current check allows

    mswi-&gt;hart_count = ACLINT_MSWI_MAX_HARTS
    mswi-&gt;first_hartid = SBI_HARTMASK_MAX_BITS - 1.

With these values mswi_hartid2data will be accessed at index

    SBI_HARTMASK_MAX_BITS + SBI_HARTMASK_MAX_BITS - 2.

We have to check the sum of mswi-&gt;first_hartid and mswi-&gt;hart_count.

Furthermore mswi-&gt;hart_count = 0 would not make much sense.

Addresses-Coverity-ID: 1529705 ("Out-of-bounds write")
Fixes: 5a049fe1d6a5 ("lib: utils/ipi: Add ACLINT MSWI library")
Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: Improve fdt_ipi</title>
<updated>2023-05-26T07:13:25Z</updated>
<author>
<name>Xiang W</name>
<email>wxjstz@126.com</email>
</author>
<published>2023-05-22T05:18:08Z</published>
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<id>urn:sha1:9a0bdd0c844ea87a7b83c313e1dd8e8152d508e7</id>
<content type='text'>
Remove dummy driver. Optimize fdt_ipi_cold_init to exit the loop
early.

Signed-off-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: Add M-mode {R/W} flags to the MMIO regions</title>
<updated>2023-01-09T12:34:28Z</updated>
<author>
<name>Himanshu Chauhan</name>
<email>hchauhan@ventanamicro.com</email>
</author>
<published>2023-01-09T05:20:42Z</published>
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<id>urn:sha1:59a08cd7d632bb2394a29956497dfe7829099997</id>
<content type='text'>
Add the M-mode readable/writable flags to mmio regions
of various drivers.

Signed-off-by: Himanshu Chauhan &lt;hchauhan@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Tested-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/ipi: mswi: add T-Head C9xx CLINT compatible</title>
<updated>2022-12-17T05:31:00Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>uwu@icenowy.me</email>
</author>
<published>2022-12-12T08:22:36Z</published>
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<id>urn:sha1:a8ee82cd8c008f09c91b5c307de4c9b37660ff71</id>
<content type='text'>
Althoug the MTIMER part of a C9xx CLINT differs from a SiFive one, the
MSWI part is compliant.

Add T-Head C9xx CLINT compatible string to fdt_ipi_mswi code, sharing
the same codepath with SiFive CLINT.

Signed-off-by: Icenowy Zheng &lt;uwu@icenowy.me&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/ipi: Add Andes fdt ipi driver support</title>
<updated>2022-10-23T05:01:01Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2022-10-14T00:32:50Z</published>
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<id>urn:sha1:ce7c490719ed4e268979c8b6b54a5252396fbb3b</id>
<content type='text'>
Move Andes PLICSW ipi device to fdt ipi framework, this patch is based
on Leo's modified IPI scheme on PLICSW.

Current IPI scheme uses bit 0 of pending reigster on PLICSW to send IPI
from hart 0 to hart 7, but bit 0 needs to be hardwired to 0 according
to spec. After some investigation, self-IPI seems to be seldom or never
used, so we re-order the IPI scheme to support 8 core platforms.

dts example (Quad-core AX45MP):

  plicsw: interrupt-controller@e6400000 {
          compatible = "andestech,plicsw";
          reg = &lt;0x00000000 0xe6400000 0x00000000 0x00400000&gt;;
          interrupts-extended = &lt;&amp;CPU0_intc 3
                                 &amp;CPU1_intc 3
                                 &amp;CPU2_intc 3
                                 &amp;CPU3_intc 3&gt;;
          interrupt-controller;
          #address-cells = &lt;2&gt;;
          #interrupt-cells = &lt;2&gt;;
  };

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/fdt: Use kconfig for enabling/disabling</title>
<updated>2022-08-08T04:04:08Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-08-08T04:04:08Z</published>
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<id>urn:sha1:68d7b85ec75119787d7c672062de5d29156c44be</id>
<content type='text'>
We update FDT support makefile to use kconfig for enabling/disabling.
To avoid compilation errors, we also enable FDT for each platform.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Acked-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Tested-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/ipi: Use kconfig for enabling/disabling drivers</title>
<updated>2022-08-08T04:03:45Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-08-08T04:03:45Z</published>
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<id>urn:sha1:76af9d40da21c4c67efb7730de263f914452fca0</id>
<content type='text'>
We update ipi drivers makefile to use kconfig for enabling/disabling
drivers. To avoid compile errors, we also enable appropriate ipi
drivers for each platform.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Acked-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Tested-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Remove Allwinner D1 CLINT compatibles</title>
<updated>2022-06-22T05:25:37Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2022-06-22T04:57:42Z</published>
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<id>urn:sha1:6f1fe98c2f565a394f258178b0daa3843672395c</id>
<content type='text'>
The allwinner,sun20i-d1-clint compatible string is not documented in any
official binding, so it should not be used by drivers.

The MSWI in the D1 CLINT is compatible with the ACLINT specification, so
it can take advantage of generic driver support. However, that is only
possible if the MSWI and MTIMER are split into separate DT nodes. This
means the final binding for this device is likely to be incompatible
with what is implemented here.

Remove this compatible string from the driver to prevent it from
appearing in a stable version and causing future issues.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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