opensbi.git/lib/utils/ipi, branch v1.4

lib: utils/timer: mtimer: only use regname for aclint

2023-12-27T06:27:33Z

The parser will fail if the timer is clint timer and has regname property. As the regname is only meaningful for aclint, it is more robust to only check regname for aclint timer. Fixes: 6112d58 ("lib: utils/fdt: Allow to use reg-names when parsing ACLINT") Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel

lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme

2023-12-06T11:53:27Z

The old scheme doesn't allow sending hart0 self-IPI as the corresponding bit on pending register is hardwired to 0, this could lead to unhandle IPIs on SMP systems, esp. on single-core. Furthermore, the limitation of old scheme is 8-core, instead of reserving source hart information, we assign bit (x + 1) as the enable and pending bit of hartx, this also expands the bootable hart number. The following diagram shows the enable bits of the new scheme on 32-core Andes platform. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> To send IPI to hart0, for example, another hart (including hart0 itself) will set bit 1 of first word on the pending register. We also fix indentation in andes_plicsw.h along with this patch. Fixes: ce7c490719ed ("lib: utils/ipi: Add Andes fdt ipi driver support") Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin Reviewed-by: Randolph Reported-by: Lad Prabhakar Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005665.html Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar Reviewed-by: Anup Patel

lib: sbi: Allow relaxed MMIO writes in device ipi_clear() callback

2023-11-26T13:15:08Z

Currently, there are no barriers before or after the ipi_clear() device callback which forces ipi_clear() device callback to always use non-relaxed MMIO writes. Instead of above, we use wmb() in after the ipi_clear() device callback which pairs with the wmb() done before the ipi_send() device callback. This also allows device ipi_clear() callback to use relaxed MMIO writes. Signed-off-by: Anup Patel Reported-by: Bo Gan

lib: sbi: Allow relaxed MMIO writes in device ipi_send() callback

2023-11-26T13:15:06Z

Currently, we have a smp_wmb() between atomic_raw_set_bit() and ipi_send() device callback whereas the MMIO writes done by the device ipi_send() callback will also include a barrier. We can avoid unnecessary/redundant barriers described above by allowing relaxed MMIO writes in device ipi_send() callback. To achieve this, we simply use wmb() instead of smp_wmb() before calling device ipi_send(). Signed-off-by: Anup Patel Reported-by: Bo Gan

lib: utils/ipi: mswi: add separate T-Head C9xx CLINT mswi compatible

2023-11-16T11:25:28Z

Like the mtimer of T-HEAD C9xx clint, the mswi also needs new compatible string to avoid misuse. Signed-off-by: Inochi Amaoto Link: https://lore.kernel.org/linux-riscv/1f6b82a1864477a51db33d3f295889ff985b497b.1696433229.git.unicorn_wang@outlook.com/ Reviewed-by: Guo Ren Reviewed-by: Anup Patel

lib: utils: timer/ipi: Update memregion flags for PLMT and PLICSW

2023-10-06T11:23:26Z

This patch adds unspecified permission flags for the PLICSW region and updates the permission of the PLMT region. With this update, both regions will become M-mode only read/write regions in the root domain. Domain0 Region00: 0x00000000f0300000-0x00000000f0300fff M: (I,R,W) S/U: (R,W) Domain0 Region01: 0x0000000000040000-0x000000000005ffff M: (R,W) S/U: () Domain0 Region02: 0x0000000000000000-0x000000000003ffff M: (R,X) S/U: () > Domain0 Region03: 0x00000000e6000000-0x00000000e60fffff M: (I,R,W) S/U: () > Domain0 Region04: 0x00000000e6400000-0x00000000e67fffff M: (I,R,W) S/U: () Domain0 Region05: 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) The PMP rules of AE350-AX65 (single-core) w/ Smepmp: p/x $pmpcfg0 $1 = {0x1f9b9b9d9b1e00, pmp0cfg = {0x0}, L--AAXWR pmp1cfg = {0x1e} (00011110), pmpaddr1: 0xf0300000 ~ 0xf0300fff (UART1) pmp2cfg = {0x9b} (10011011), pmpaddr2: 0x40000 ~ 0x5ffff pmp3cfg = {0x9d} (10011101), pmpaddr3: 0x0 ~ 0x3ffff pmp4cfg = {0x9b} (10011011), pmpaddr4: 0xe6000000 ~ 0xe60fffff (PLMT) pmp5cfg = {0x9b} (10011011), pmpaddr5: 0xe6400000 ~ 0xe67fffff (PLICSW) pmp6cfg = {0x1f} (00011111), pmpaddr6: 0x0 ~ 0xffffffffff pmp7cfg = {0x0 }} The PMP rules of AE350-AX45MP (qual-core) w/o Smepmp: p/x $pmpcfg0 $1 = {0x1f181818181b, L--AAXWR pmp0cfg = {0x1b}, (00011011), pmpaddr0: 0xf0300000 ~ 0xf0300fff (UART1) pmp1cfg = {0x18}, (00011000), pmpaddr1: 0x40000 ~ 0x5ffff pmp2cfg = {0x18}, (00011000), pmpaddr2: 0x0 ~ 0x3ffff pmp3cfg = {0x18}, (00011000), pmpaddr3: 0xe6000000 ~ 0xe60fffff (PLMT) pmp4cfg = {0x18}, (00011000), pmpaddr4: 0xe6400000 ~ 0xe67fffff (PLICSW) pmp5cfg = {0x1f}, (00011111), pmpaddr5: 0x0 ~ 0x1ffffffff pmp6cfg = {0x0 }} Note that starting from this patch, we restrict the S/U-mode read permission to the PLMT region, since we should read the TIME CSR in a lower privilege mode. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

lib: sbi: Prefer hartindex over hartid in IPI framework

2023-09-24T06:09:38Z

Let us prefer hartindex over hartid in IPI framework which in-turn forces IPI users to also prefer hartindex. Signed-off-by: Anup Patel

lib: utils: Fix sbi_hartid_to_scratch() usage in ACLINT drivers

2023-07-09T05:34:57Z

The cold_init() functions of ACLINT drivers should skip the HART if sbi_hartid_to_scratch() returns NULL because we might be dealing with a HART that is disabled in the device tree. Signed-off-by: Anup Patel Reviewed-by: Xiang W

lib: utils/ipi: Use scratch space to save per-HART MSWI pointer

2023-06-05T10:32:59Z

Instead of using a global array indexed by hartid, we should use scratch space to save per-HART MSWI pointer. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones

lib: utils/ipi: Use heap in ACLINT MSWI driver

2023-06-05T10:25:56Z

Let's use heap allocation in ACLINT MSWI driver instead of using a fixed size global array. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones