opensbi.git/lib/utils/irqchip/aplic.c, branch master

lib: utils/irqchip/aplic: add MSI mode support with IMSIC parent linking

2026-07-22T07:38:13Z

Add parent_unique_id fields to struct aplic_data for IMSIC parent linking in MSI mode. Store parent IMSIC unique_id during FDT parsing of the APLIC node. Add aplic_is_msi_mode() complementing aplic_is_direct_mode() to consolidate delivery mode detection. Add APLIC_TARGET_EIID() macro for packing the EIID field into the TARGET register. Add parent_unique_id and parent_irq_map fields to struct aplic_data. parent_unique_id identifies the upstream IMSIC irqchip device resolved via sbi_irqchip_find_device() during hwirq_setup. parent_irq_map is a per-source array allocated at cold init time to track the EIID assigned by the IMSIC for each APLIC source. Restore aplic_writel_msicfg() and re-introduce MSI address register programming in aplic_init(), gated on aplic_is_msi_mode(). Set the DOMAINCFG_DM bit to switch the hardware to MSI delivery mode when no IDC structures are present. Add aplic_program_msi_target() to pack hart_index, guest_index, and EIID into the APLIC_TARGET register. Add aplic_write_msi() as the sbi_irqchip write_msi callback that extracts EIID and hart_index from the MSI message and calls aplic_program_msi_target(). Add aplic_msi_callback() as the MSI receive callback that dispatches to sbi_irqchip_process_hwirq() on the APLIC chip. Extend aplic_hwirq_setup() with an MSI path that resolves the parent IMSIC chip by parent_unique_id, registers an MSI route via sbi_irqchip_register_msi(), and stores the allocated EIID in parent_irq_map for the source being configured. Extend aplic_hwirq_set_affinity() with an MSI path that delegates affinity reprogramming to the parent IMSIC chip via sbi_irqchip_set_affinity() using the stored parent_irq_map entry. Guard warm_init, process_hwirqs, and hwirq_eoi with early returns in MSI mode as interrupt delivery and acknowledgement are handled by the IMSIC in that configuration. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-3-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/aplic: implement direct mode irqchip callbacks

2026-07-22T07:37:40Z

Add inline register accessors (aplic_sourcecfg_write/read, aplic_target_write, aplic_irq_setie/clrie/clrip, aplic_idc_base/ read/write) to consolidate all MMIO access behind typed helpers and eliminate open-coded address arithmetic throughout the driver. Add field-packing macros APLIC_TARGET_HART_IDX, APLIC_TARGET_IPRIO, and APLIC_TARGET_GUEST_IDX for constructing APLIC_TARGET register values. Add aplic_is_direct_mode() mode helper, aplic_hwirq_flags_to_sourcecfg() to map generic hwirq flags to APLIC source modes, aplic_hwirq_is_delegated() to detect S-mode delegated sources, aplic_find_idc_index() to map a hart index to its IDC slot, and aplic_first_target_hart() to select the first available IDC hart for initial interrupt targeting. Implement the full sbi_irqchip callback set for direct (IDC) mode: - warm_init: enables IDC interrupt delivery and threshold per hart - process_hwirqs: reads TOPI and dispatches via sbi_irqchip_process_hwirq, skipping delegated sources - hwirq_setup: programs sourcecfg from hwirq_flags and sets the TARGET register to the first available IDC hart - hwirq_cleanup: clears IE, IP, sourcecfg, and TARGET on teardown - hwirq_eoi: reads CLAIMI to acknowledge the interrupt on the IDC - hwirq_set_affinity: reprograms TARGET to the specified hart index - hwirq_mask/unmask: clears/sets IE via CLRIENUM/SETIENUM Register the irqchip device and populate target_harts from idc_map only when targets_mmode is set in aplic_cold_irqchip_init(). Co-developed-by: Raymond Mao Signed-off-by Raymond Mao Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-2-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Allow irqchip drivers advertise capabilities

2026-06-10T12:43:10Z

Extend struct sbi_irqchip_device to allow irqchip drivers advertise interrupt controller capabilities (such as wired interrupt, MSIs, etc). This further allows other parts of OpenSBI to lookup irqchip devices based on capabilities. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260608125257.3220114-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Allow registering interrupt handlers

2026-03-22T05:25:58Z

To handle external interrupts in M-mode, the sbi_irqchip framework must allow registering interrupt handlers from device drivers. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260213055342.3124872-9-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Associate 32-bit unique ID for each irqchip device

2026-03-22T05:25:08Z

Allow locating irqchip device instance using a unique 32-bit ID. This 32-bit unique ID can be set by the irqchip driver at the time of adding irqchip device. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260213055342.3124872-8-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Support irqchip device targetting subset of harts

2026-03-22T05:23:33Z

It is possible to have platform where an irqchip device targets a subset of harts and there are multiple irqchip devices to cover all harts. To support this scenario: 1) Add target_harts hartmask to struct sbi_irqchip_device which represents the set of harts targetted by the irqchip device 2) Call warm_init() and process_hwirqs() callbacks of an irqchip device on a hart only if irqchip device targets that particular hart Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260213055342.3124872-6-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip: Add APLIC restore function

2025-10-28T05:57:59Z

Since the APLIC may enter a reset state upon system wake-up from a platform low power state, adding a restore function to reinitialize the APLIC. Reviewed-by: Yong-Xuan Wang Reviewed-by: Cyan Yang Reviewed-by: Anup Patel Signed-off-by: Nick Hu Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-7-69a132447d8a@sifive.com Signed-off-by: Anup Patel

lib: utils/irqchip: fix aplic lock mechanism in xmsiaddrcfg(h)

2025-09-30T11:54:13Z

The section 4.5.4 "Supervisor MSI address configuration (smsiaddrcfg and smsiaddrcfgh)" of the AIA specification states that: "If register mmsiaddrcfgh of the domain has bit L set to one, then smsiaddrcfg and smsiaddrcfgh are locked as read-only alongside mmsiaddrcfg and mmsiaddrcfgh." In other words, the L bit is not defined for smsiaddrcfg[h] registers so fix aplic_writel_msicfg() accordingly. Signed-off-by: Yang Jialong Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250806032924.3532975-1-z_bajeer@yeah.net Signed-off-by: Anup Patel

lib: utils: Fix irqchip registration for PLIC and APLIC

2024-12-24T08:36:09Z

Currently, the same irqchip instance is registered for multiple PLIC and APLIC instances which causes the sbi_list_for_each_entry() loop in the sbi_irqchip_init() to hang at boot-time. To address the above issue, register a separate irqchip instance for each PLIC and APLIC instance. Fixes: 2dd6eaf68055 ("lib: sbi_irqchip: Call driver warm_init from SBI core") Reported-by: Himanshu Chauhan Signed-off-by: Anup Patel Reviewed-by: Himanshu Chauhan

lib: sbi_irqchip: Register devices during cold init

2024-11-28T06:07:25Z

Have the SBI irqchip core keep track of registered irqchip devices. This is useful for any callbacks the irqchip driver may have, such as for warm initialization, the external interrupt handler function, and any future support for handling external interrupts (beyond IPIs) in M-mode. This improves on the tracking done in fdt_irqchip.c, as it tracks device instances, not just drivers, so callbacks can target a specific device. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel