opensbi.git/lib/utils/irqchip/imsic.c, branch master

lib: utils/irqchip/imsic: track IRQ enable state and restore EIE on warm init

2026-07-22T07:50:20Z

Add an irq_state field to struct sbi_irqchip_hwirq_data with a single IRQ_ENABLED flag (bit 0) to track whether a hardware interrupt has been enabled via the irqchip framework. Set IRQ_ENABLED in sbi_irqchip_unmask_hwirq() when the unmask callback is invoked. Add sbi_irqchip_get_irq_state() as a private inline accessor and expose sbi_irqchip_is_irq_enabled() as a public API for drivers to query the enabled state of a hardware interrupt by chip pointer and hwirq number. Refactor imsic_local_eix_update() to operate on a single interrupt ID instead of a base+count range, simplifying the CSR bit manipulation to a direct BIT(id) write without the inner loop. Update all call sites accordingly. Use sbi_irqchip_is_irq_enabled() in imsic_warm_irqchip_init() to restore per-EIID EIE CSR state on warm boot and HSM resume based on the saved irq_state, replacing the previous blanket disable of all interrupts. This ensures that EIIDs enabled during hotplug/warminit cycle are correctly re-enabled on the resuming hart without requiring software to re-register or re-unmask each interrupt. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-6-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/imsic:migrate to irqchip framework

2026-07-22T07:50:14Z

Rewrite imsic_process_hwirqs() to use container_of() for instance lookup, validate ownership via imsic_current_hart_owner(), mask IMSIC_TOPEI_ID_MASK on the raw CSR value, and dispatch non-IPI EIIDs through sbi_irqchip_process_hwirq() instead of an open-coded switch. Rewrite imsic_warm_irqchip_init() to resolve the imsic_data instance via container_of() from the sbi_irqchip_device pointer, and skip initialization silently for harts not owned by this instance. Extend the sbi_irqchip callback set: - hwirq_setup: registers sbi_irqchip_raw_handler_default for the EIID - hwirq_cleanup: clears EIE and EIP bits for the EIID on the owner hart - hwirq_eoi: no-op as claim/ack is already performed by CSR_MTOPEI read in imsic_process_hwirqs() - hwirq_set_affinity: reprograms the upstream MSI source via imsic_program_msi() to retarget the interrupt to the new hart - hwirq_mask: clears the EIE bit for the EIID on the owner hart - hwirq_unmask: sets the EIE bit for the EIID on the owner hart, skipping IPI (EIID 1) and non-owner harts Add imsic_compose_msi_msg() to compute the MMIO target address for a given hart and EIID by walking the imsic_regs array and applying file and guest index offsets. Add imsic_program_msi() that composes an MSI message and delivers it to the upstream interrupt source via sbi_irqchip_write_msi(), enabling APLIC TARGET register programming from the IMSIC driver. Migrate imsic_cold_irqchip_init() to the instance-based model: preserve any pre-configured target_harts mask set by platform or FDT code before applying the imsic_device template, falling back to sbi_hartmask_set_all() only when no mask was provided. Register the irqchip and reserved EIIDs on the embedded irqchip rather than the global singleton. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-5-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/imsic: embed sbi_irqchip_device in imsic data

2026-07-22T07:38:15Z

Embed sbi_irqchip_device in struct imsic_data to enable instance-based irqchip registration, replacing the previous global imsic_device singleton. Include sbi_irqchip.h from imsic.h to make the embedded struct visible to consumers. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-4-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Allow irqchip drivers advertise capabilities

2026-06-10T12:43:10Z

Extend struct sbi_irqchip_device to allow irqchip drivers advertise interrupt controller capabilities (such as wired interrupt, MSIs, etc). This further allows other parts of OpenSBI to lookup irqchip devices based on capabilities. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260608125257.3220114-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Allow marking hardware interrupts as reserved

2026-05-12T04:25:58Z

Some of the hardware interrupts may be special so allow irqchip drivers to make these hardware interrupts as reserved. Introduce sbi_irqchip_register_reserved() for this purpose. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260423052339.356900-5-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Allow interrupt client to specify line sensing

2026-05-12T04:25:58Z

The interrupt client should be allowed to specify the line sensing type of the hwirqs for which it is registering handler. To support this, add hwirq_flags parameter to hwirq_setup() callback provided by the irqchip driver. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260423052339.356900-4-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Allow registering interrupt handlers

2026-03-22T05:25:58Z

To handle external interrupts in M-mode, the sbi_irqchip framework must allow registering interrupt handlers from device drivers. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260213055342.3124872-9-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Associate 32-bit unique ID for each irqchip device

2026-03-22T05:25:08Z

Allow locating irqchip device instance using a unique 32-bit ID. This 32-bit unique ID can be set by the irqchip driver at the time of adding irqchip device. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260213055342.3124872-8-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Support irqchip device targetting subset of harts

2026-03-22T05:23:33Z

It is possible to have platform where an irqchip device targets a subset of harts and there are multiple irqchip devices to cover all harts. To support this scenario: 1) Add target_harts hartmask to struct sbi_irqchip_device which represents the set of harts targetted by the irqchip device 2) Call warm_init() and process_hwirqs() callbacks of an irqchip device on a hart only if irqchip device targets that particular hart Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260213055342.3124872-6-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Rename irq_handle() callback to process_hwirqs()

2026-03-22T05:22:41Z

The irq_handle() callback of irqchip device is meant to process hardware interrupt of the irqchip hence rename it accordingly. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260213055342.3124872-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel