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<title>opensbi.git/lib/utils/irqchip/imsic.c, branch v1.3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/lib/utils/irqchip/imsic.c?h=v1.3</id>
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<updated>2023-06-06T10:31:14Z</updated>
<entry>
<title>lib: utils/irqchip: Use scratch space to save per-HART IMSIC pointer</title>
<updated>2023-06-06T10:31:14Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-04-20T04:48:08Z</published>
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<id>urn:sha1:355796c5bc1906d749850e4215e0f7f53802ba5b</id>
<content type='text'>
Instead of using a global array indexed by hartid, we should use
scratch space to save per-HART IMSIC pointer and IMSIC file number.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils: Add M-mode {R/W} flags to the MMIO regions</title>
<updated>2023-01-09T12:34:28Z</updated>
<author>
<name>Himanshu Chauhan</name>
<email>hchauhan@ventanamicro.com</email>
</author>
<published>2023-01-09T05:20:42Z</published>
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<id>urn:sha1:59a08cd7d632bb2394a29956497dfe7829099997</id>
<content type='text'>
Add the M-mode readable/writable flags to mmio regions
of various drivers.

Signed-off-by: Himanshu Chauhan &lt;hchauhan@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Tested-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: Remove CSRs that set/clear an IMSIC interrupt file bits</title>
<updated>2022-06-21T03:14:45Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-06-16T11:58:56Z</published>
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<id>urn:sha1:c6530012d46ed9c9655c426450bfa3aabcc0eadd</id>
<content type='text'>
Based on architecture review committee feedback, the [m|s|vs]seteienum,
[m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are
removed in the latest AIA draft v0.3.0 specification.
(Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31)

These CSRs were mostly for software convenience and software can always
use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt
file bits.

We update the IMSIC programming as-per above to match the latest AIA
draft specification.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add a simple external interrupt handling framework</title>
<updated>2022-02-28T04:13:12Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-02-18T17:48:41Z</published>
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<id>urn:sha1:f3f4604c196dea70b0bb64aba747aa6d7a9e244f</id>
<content type='text'>
Currently, the external interrupt handling is scattered between
sbi_init and sbi_trap. This patch moves all external interrupt
handling into a simple framework called sbi_irqchip.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Add IMSIC library</title>
<updated>2022-02-15T15:06:24Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2021-04-20T11:03:40Z</published>
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<id>urn:sha1:9f73669959dd8ec2f1261b639f9540799dc976a1</id>
<content type='text'>
We add simple IMSIC library which is independent of hardware description
format (FDT or ACPI). This IMSIC library can be used by custom OpenSBI
platform support to setup IMSIC for external interrupts.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
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