<feed xmlns='http://www.w3.org/2005/Atom'>
<title>opensbi.git/lib/utils/irqchip/imsic.c, branch v1.6</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/lib/utils/irqchip/imsic.c?h=v1.6</id>
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<updated>2024-11-28T06:21:56Z</updated>
<entry>
<title>lib: sbi_irqchip: Set the IRQ handler when registering a chip</title>
<updated>2024-11-28T06:21:56Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:10Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=111772353f4a334dfc4a94a17ebbec8e3edc0b5e'/>
<id>urn:sha1:111772353f4a334dfc4a94a17ebbec8e3edc0b5e</id>
<content type='text'>
In addition to saving some code size, this moves the decision about
setting the top-level external interrupt handler to the irqchip core,
not the specific driver, which would be needed to support chained
interrupt handlers.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_irqchip: Call driver warm_init from SBI core</title>
<updated>2024-11-28T06:10:17Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:08Z</published>
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<id>urn:sha1:2dd6eaf680556e763a85b0b4ae180391e2671854</id>
<content type='text'>
Currently, each platform keeps track of which irqchip driver is in use
and calls its warm init function. Since the generic platform may use
multiple irqchip drivers, it has logic to track an array of drivers.

The code is simplified and made common across platforms by treating warm
init and exit as properties of the driver, not the platform. Then the
platform's only role is to select and prepare a driver during cold boot.

For now, only add a .warm_init hook, since none of the existing drivers
need an .exit hook. It could be added in the future if needed.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_irqchip: Register devices during cold init</title>
<updated>2024-11-28T06:07:25Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:07Z</published>
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<id>urn:sha1:e3e5686ef903d037c6b5835a6752481a07faf99f</id>
<content type='text'>
Have the SBI irqchip core keep track of registered irqchip devices. This
is useful for any callbacks the irqchip driver may have, such as for
warm initialization, the external interrupt handler function, and any
future support for handling external interrupts (beyond IPIs) in M-mode.

This improves on the tracking done in fdt_irqchip.c, as it tracks device
instances, not just drivers, so callbacks can target a specific device.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Use sbi_domain_root_add_memrange() for IMSIC</title>
<updated>2024-10-25T17:29:56Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2024-09-20T08:45:55Z</published>
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<id>urn:sha1:abc68e881da1f4168c698d35643e139ea51ac2e9</id>
<content type='text'>
The sbi_domain_root_add_memrange() should be preferred for creating
multiple memregions over a range. Update IMSIC driver to use
sbi_domain_root_add_memrange() instead of explicitly registering
memregions.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Look up IMSIC data by hart index</title>
<updated>2024-09-25T12:36:59Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-08-30T15:49:09Z</published>
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<id>urn:sha1:7f5fa9f9a48d3d4f6379ce207f50e8347cad3a14</id>
<content type='text'>
This avoids needing to map a hartid to a hart index.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: Delete redundant `ulong`</title>
<updated>2024-08-24T09:12:14Z</updated>
<author>
<name>Zhang RunMin</name>
<email>runmin.zhang@ingenic.com</email>
</author>
<published>2024-08-14T13:23:01Z</published>
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<id>urn:sha1:ef4520b1c63fc2770b10d952a800f9734f861b0a</id>
<content type='text'>
In `csr_read_allowed` and `csr_write_allowed` macros, has already
converted second param to `ulong`. So delete redundant `ulong`
where uses csr_read/write_allowed macros.

Signed-off-by: Zhang RunMin &lt;runmin.zhang@ingenic.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Add sanity checks in imsic_get_data() and imsic_get_target_file()</title>
<updated>2024-05-23T05:21:29Z</updated>
<author>
<name>Cyan Yang</name>
<email>cyan.yang@sifive.com</email>
</author>
<published>2024-05-16T08:32:43Z</published>
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<id>urn:sha1:858754a54470ad0dbbced7838b17054ccd3b96de</id>
<content type='text'>
Add extra sanity checks to prevent the caller getting the invalid result from
imsic_get_data() or imsic_get_target_file() when imsic is not initialized
correctly.

Signed-off-by: Cyan Yang &lt;cyan.yang@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Check before initializing imsic</title>
<updated>2024-05-16T04:51:16Z</updated>
<author>
<name>Cheng Yang</name>
<email>yangcheng.work@foxmail.com</email>
</author>
<published>2024-05-15T06:15:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=e3a30a2c918aae79d4cc403d474c3d2872a9063c'/>
<id>urn:sha1:e3a30a2c918aae79d4cc403d474c3d2872a9063c</id>
<content type='text'>
The current mlevel imsic check is only for the platform, which
may cause hart without imsic in the platform to trigger an
illegal instruction exception when initializing imsic. For
example, the platform contains a management hart that only
supports wired interrupts.

This patch will check if each hart supports Smaia extension
before doing imsic initialization to avoid triggering illegal
instruction exceptions.

Signed-off-by: Cheng Yang &lt;yangcheng.work@foxmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Remove regs paramter of sbi_irqchip_process()</title>
<updated>2024-03-19T06:01:33Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2024-03-11T12:23:41Z</published>
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<id>urn:sha1:d84e7eb7f0848225e10131ca4b9e1571d78cdabd</id>
<content type='text'>
The irqchip handlers will typically not need pointer to trap registers
so remove regs parameter of sbi_irqchip_process().

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Tested-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Clément Léger &lt;cleger@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Allow relaxed MMIO writes in device ipi_send() callback</title>
<updated>2023-11-26T13:15:06Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-11-21T09:19:42Z</published>
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<id>urn:sha1:f520256d03da84e7ff8bddd084ef873192f46304</id>
<content type='text'>
Currently, we have a smp_wmb() between atomic_raw_set_bit() and
ipi_send() device callback whereas the MMIO writes done by the
device ipi_send() callback will also include a barrier.

We can avoid unnecessary/redundant barriers described above by
allowing relaxed MMIO writes in device ipi_send() callback. To
achieve this, we simply use  wmb() instead of smp_wmb() before
calling device ipi_send().

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reported-by: Bo Gan &lt;ganboing@gmail.com&gt;
</content>
</entry>
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