opensbi.git/lib/utils/irqchip, branch master

lib: utils/irqchip/imsic: track IRQ enable state and restore EIE on warm init

2026-07-22T07:50:20Z

Add an irq_state field to struct sbi_irqchip_hwirq_data with a single IRQ_ENABLED flag (bit 0) to track whether a hardware interrupt has been enabled via the irqchip framework. Set IRQ_ENABLED in sbi_irqchip_unmask_hwirq() when the unmask callback is invoked. Add sbi_irqchip_get_irq_state() as a private inline accessor and expose sbi_irqchip_is_irq_enabled() as a public API for drivers to query the enabled state of a hardware interrupt by chip pointer and hwirq number. Refactor imsic_local_eix_update() to operate on a single interrupt ID instead of a base+count range, simplifying the CSR bit manipulation to a direct BIT(id) write without the inner loop. Update all call sites accordingly. Use sbi_irqchip_is_irq_enabled() in imsic_warm_irqchip_init() to restore per-EIID EIE CSR state on warm boot and HSM resume based on the saved irq_state, replacing the previous blanket disable of all interrupts. This ensures that EIIDs enabled during hotplug/warminit cycle are correctly re-enabled on the resuming hart without requiring software to re-register or re-unmask each interrupt. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-6-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/imsic:migrate to irqchip framework

2026-07-22T07:50:14Z

Rewrite imsic_process_hwirqs() to use container_of() for instance lookup, validate ownership via imsic_current_hart_owner(), mask IMSIC_TOPEI_ID_MASK on the raw CSR value, and dispatch non-IPI EIIDs through sbi_irqchip_process_hwirq() instead of an open-coded switch. Rewrite imsic_warm_irqchip_init() to resolve the imsic_data instance via container_of() from the sbi_irqchip_device pointer, and skip initialization silently for harts not owned by this instance. Extend the sbi_irqchip callback set: - hwirq_setup: registers sbi_irqchip_raw_handler_default for the EIID - hwirq_cleanup: clears EIE and EIP bits for the EIID on the owner hart - hwirq_eoi: no-op as claim/ack is already performed by CSR_MTOPEI read in imsic_process_hwirqs() - hwirq_set_affinity: reprograms the upstream MSI source via imsic_program_msi() to retarget the interrupt to the new hart - hwirq_mask: clears the EIE bit for the EIID on the owner hart - hwirq_unmask: sets the EIE bit for the EIID on the owner hart, skipping IPI (EIID 1) and non-owner harts Add imsic_compose_msi_msg() to compute the MMIO target address for a given hart and EIID by walking the imsic_regs array and applying file and guest index offsets. Add imsic_program_msi() that composes an MSI message and delivers it to the upstream interrupt source via sbi_irqchip_write_msi(), enabling APLIC TARGET register programming from the IMSIC driver. Migrate imsic_cold_irqchip_init() to the instance-based model: preserve any pre-configured target_harts mask set by platform or FDT code before applying the imsic_device template, falling back to sbi_hartmask_set_all() only when no mask was provided. Register the irqchip and reserved EIIDs on the embedded irqchip rather than the global singleton. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-5-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/imsic: embed sbi_irqchip_device in imsic data

2026-07-22T07:38:15Z

Embed sbi_irqchip_device in struct imsic_data to enable instance-based irqchip registration, replacing the previous global imsic_device singleton. Include sbi_irqchip.h from imsic.h to make the embedded struct visible to consumers. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-4-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/aplic: add MSI mode support with IMSIC parent linking

2026-07-22T07:38:13Z

Add parent_unique_id fields to struct aplic_data for IMSIC parent linking in MSI mode. Store parent IMSIC unique_id during FDT parsing of the APLIC node. Add aplic_is_msi_mode() complementing aplic_is_direct_mode() to consolidate delivery mode detection. Add APLIC_TARGET_EIID() macro for packing the EIID field into the TARGET register. Add parent_unique_id and parent_irq_map fields to struct aplic_data. parent_unique_id identifies the upstream IMSIC irqchip device resolved via sbi_irqchip_find_device() during hwirq_setup. parent_irq_map is a per-source array allocated at cold init time to track the EIID assigned by the IMSIC for each APLIC source. Restore aplic_writel_msicfg() and re-introduce MSI address register programming in aplic_init(), gated on aplic_is_msi_mode(). Set the DOMAINCFG_DM bit to switch the hardware to MSI delivery mode when no IDC structures are present. Add aplic_program_msi_target() to pack hart_index, guest_index, and EIID into the APLIC_TARGET register. Add aplic_write_msi() as the sbi_irqchip write_msi callback that extracts EIID and hart_index from the MSI message and calls aplic_program_msi_target(). Add aplic_msi_callback() as the MSI receive callback that dispatches to sbi_irqchip_process_hwirq() on the APLIC chip. Extend aplic_hwirq_setup() with an MSI path that resolves the parent IMSIC chip by parent_unique_id, registers an MSI route via sbi_irqchip_register_msi(), and stores the allocated EIID in parent_irq_map for the source being configured. Extend aplic_hwirq_set_affinity() with an MSI path that delegates affinity reprogramming to the parent IMSIC chip via sbi_irqchip_set_affinity() using the stored parent_irq_map entry. Guard warm_init, process_hwirqs, and hwirq_eoi with early returns in MSI mode as interrupt delivery and acknowledgement are handled by the IMSIC in that configuration. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-3-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/aplic: implement direct mode irqchip callbacks

2026-07-22T07:37:40Z

Add inline register accessors (aplic_sourcecfg_write/read, aplic_target_write, aplic_irq_setie/clrie/clrip, aplic_idc_base/ read/write) to consolidate all MMIO access behind typed helpers and eliminate open-coded address arithmetic throughout the driver. Add field-packing macros APLIC_TARGET_HART_IDX, APLIC_TARGET_IPRIO, and APLIC_TARGET_GUEST_IDX for constructing APLIC_TARGET register values. Add aplic_is_direct_mode() mode helper, aplic_hwirq_flags_to_sourcecfg() to map generic hwirq flags to APLIC source modes, aplic_hwirq_is_delegated() to detect S-mode delegated sources, aplic_find_idc_index() to map a hart index to its IDC slot, and aplic_first_target_hart() to select the first available IDC hart for initial interrupt targeting. Implement the full sbi_irqchip callback set for direct (IDC) mode: - warm_init: enables IDC interrupt delivery and threshold per hart - process_hwirqs: reads TOPI and dispatches via sbi_irqchip_process_hwirq, skipping delegated sources - hwirq_setup: programs sourcecfg from hwirq_flags and sets the TARGET register to the first available IDC hart - hwirq_cleanup: clears IE, IP, sourcecfg, and TARGET on teardown - hwirq_eoi: reads CLAIMI to acknowledge the interrupt on the IDC - hwirq_set_affinity: reprograms TARGET to the specified hart index - hwirq_mask/unmask: clears/sets IE via CLRIENUM/SETIENUM Register the irqchip device and populate target_harts from idc_map only when targets_mmode is set in aplic_cold_irqchip_init(). Co-developed-by: Raymond Mao Signed-off-by Raymond Mao Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-2-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Allow irqchip drivers advertise capabilities

2026-06-10T12:43:10Z

Extend struct sbi_irqchip_device to allow irqchip drivers advertise interrupt controller capabilities (such as wired interrupt, MSIs, etc). This further allows other parts of OpenSBI to lookup irqchip devices based on capabilities. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260608125257.3220114-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Allow marking hardware interrupts as reserved

2026-05-12T04:25:58Z

Some of the hardware interrupts may be special so allow irqchip drivers to make these hardware interrupts as reserved. Introduce sbi_irqchip_register_reserved() for this purpose. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260423052339.356900-5-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Allow interrupt client to specify line sensing

2026-05-12T04:25:58Z

The interrupt client should be allowed to specify the line sensing type of the hwirqs for which it is registering handler. To support this, add hwirq_flags parameter to hwirq_setup() callback provided by the irqchip driver. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260423052339.356900-4-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Allow registering interrupt handlers

2026-03-22T05:25:58Z

To handle external interrupts in M-mode, the sbi_irqchip framework must allow registering interrupt handlers from device drivers. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260213055342.3124872-9-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: Associate 32-bit unique ID for each irqchip device

2026-03-22T05:25:08Z

Allow locating irqchip device instance using a unique 32-bit ID. This 32-bit unique ID can be set by the irqchip driver at the time of adding irqchip device. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260213055342.3124872-8-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel