opensbi.git/lib/utils/irqchip, branch v1.2

lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers

2022-12-17T03:33:30Z

Currently the context save/restore helpers writes/reads the provided array using an index whose maximum value is determined by PLIC, which potentially may disagree with the caller to these helpers. Add a parameter to ask the caller to provide the size limit of the array to ensure no out-of-bound access happens. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

lib: utils/irqchip: plic: Fix the off-by-one error in context save/restore helpers

2022-12-17T03:32:40Z

plic->num_src holds the number of interrupt sources without interrupt source 0 but the interrupt enable register includes a bit for the interrupt source 0 in the first word. Fixes: 415ecf28f7ad ("lib: irqchip/plic: Add context save/restore helpers") Signed-off-by: Bin Meng Reviewed-by: Anup Patel Reviewed-by: Samuel Holland

lib: utils/irqchip: plic: Fix the off-by-one error in plic_context_init()

2022-12-17T03:30:35Z

The number of interrupt enable register in words was once correct, but was wrongly changed to have an off-by-one error since commit 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function"). Fixes: 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function") Signed-off-by: Bin Meng Reviewed-by: Anup Patel Reviewed-by: Samuel Holland

lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers

2022-12-17T03:30:29Z

Currently the priority save/restore helpers writes/reads the provided array using an index whose maximum value is determined by PLIC, which potentially may disagree with the caller to these helpers. Add a parameter to ask the caller to provide the size limit of the array to ensure no out-of-bound access happens. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

lib: utils/irqchip: plic: Fix the off-by-one error in priority save/restore helpers

2022-12-17T03:12:21Z

Interrupt source 0 is reserved. Hence the irq should start from 1. Fixes: 2b79b694a805 ("lib: irqchip/plic: Add priority save/restore helpers") Signed-off-by: Bin Meng Reviewed-by: Anup Patel

lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100

2022-12-12T13:20:46Z

Add compatible string for Andestech NCEPLIC100 found on Renesas RZ/Five SoC which is equipped with AX45MP AndesCore. While at it drop the comma after the sentinel as it does not make sense to have a comma after a sentinel, as any new elements must be added before the sentinel. dts example (Single-core AX45MP): soc: soc { .... plic: interrupt-controller@12c00000 { compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; #interrupt-cells = <2>; #address-cells = <0>; riscv,ndev = <511>; interrupt-controller; reg = <0x0 0x12c00000 0 0x400000>; clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; power-domains = <&cpg>; resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; }; .... }; Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel Reviewed-by: Bin Meng

lib: fix irqchip_plic_update_hartid_table

2022-12-09T05:57:28Z

After determining cpu_offset we have to check this value. Addresses-Coverity-ID: 1529706 ("Logically dead code") Signed-off-by: Heinrich Schuchardt Reviewed-by: Xiang W Reviewed-by: Atish Patra Reviewed-by: Anup Patel

lib: utils/fdt: Use kconfig for enabling/disabling

2022-08-08T04:04:08Z

We update FDT support makefile to use kconfig for enabling/disabling. To avoid compilation errors, we also enable FDT for each platform. Signed-off-by: Anup Patel Tested-by: Andrew Jones Acked-by: Atish Patra Tested-by: Atish Patra

lib: utils/irqchip: Use kconfig for enabling/disabling drivers

2022-08-08T04:03:52Z

We update irqchip drivers makefile to use kconfig for enabling/disabling drivers. To avoid compile errors, we also enable appropriate irqchip drivers for each platform. Signed-off-by: Anup Patel Tested-by: Andrew Jones Acked-by: Atish Patra Tested-by: Atish Patra

lib: irqchip/plic: fix typo in plic_warm_irqchip_init

2022-06-22T05:25:27Z

The second invocation of plic_context_init() incorrectly calls the function with m_cntx_id instead of s_cntx_id. This breaks systems which only have 1 external interrupt per hart. Fixes: 8c362e7 ("lib: irqchip/plic: Factor out a context init function") Signed-off-by: Jan Remes Reviewed-by: Anup Patel Reviewed-by: Samuel Holland