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<title>opensbi.git/lib/utils/irqchip, branch v1.4</title>
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<id>http://cgit.235523.xyz/opensbi.git/atom/lib/utils/irqchip?h=v1.4</id>
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<updated>2023-12-19T10:26:37Z</updated>
<entry>
<title>lib: utils/irqchip: Add shared MMIO region for PLIC in root domain</title>
<updated>2023-12-19T10:26:37Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-12-11T08:37:56Z</published>
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<id>urn:sha1:cdebae2cc9539e2e0553b9c68eab22997c734cbb</id>
<content type='text'>
On platforms with Smepmp, the MMIO regions accessed by M-mode need
to be explicitly marked with M-mode only read/write or shared (both
(M-mode and S-mode) read/write permission.

If the above is not done then runtime PLIC access from M-mode on
platforms with Smepmp will result in access fault when further
results in CPU hotplug not working.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Allow relaxed MMIO writes in device ipi_send() callback</title>
<updated>2023-11-26T13:15:06Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-11-21T09:19:42Z</published>
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<id>urn:sha1:f520256d03da84e7ff8bddd084ef873192f46304</id>
<content type='text'>
Currently, we have a smp_wmb() between atomic_raw_set_bit() and
ipi_send() device callback whereas the MMIO writes done by the
device ipi_send() callback will also include a barrier.

We can avoid unnecessary/redundant barriers described above by
allowing relaxed MMIO writes in device ipi_send() callback. To
achieve this, we simply use  wmb() instead of smp_wmb() before
calling device ipi_send().

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reported-by: Bo Gan &lt;ganboing@gmail.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Avoid redundant writes to APLIC CLRIE register</title>
<updated>2023-11-24T07:18:41Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-11-21T06:04:14Z</published>
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<id>urn:sha1:791704cd09c019decf438f6e4f56423cc95cb66a</id>
<content type='text'>
Each APLIC CLRIE register allows disabling 32 interrupt sources at
a time by writing -1 so no need to write CLRIE register separately
for each interrupt source.

Fixes: 99792653de29 ("lib: utils/irqchip: Add APLIC initialization library")
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Prefer hartindex over hartid in IPI framework</title>
<updated>2023-09-24T06:09:38Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-09-01T12:11:07Z</published>
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<id>urn:sha1:78c667b6fc07d2ea783fbd18f43a3f8191de6164</id>
<content type='text'>
Let us prefer hartindex over hartid in IPI framework which in-turn
forces IPI users to also prefer hartindex.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Use scratch space to save per-HART IMSIC pointer</title>
<updated>2023-06-06T10:31:14Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-04-20T04:48:08Z</published>
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<id>urn:sha1:355796c5bc1906d749850e4215e0f7f53802ba5b</id>
<content type='text'>
Instead of using a global array indexed by hartid, we should use
scratch space to save per-HART IMSIC pointer and IMSIC file number.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Don't check hartid in imsic_update_hartid_table()</title>
<updated>2023-06-05T11:21:07Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-04-20T04:44:43Z</published>
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<id>urn:sha1:1df52fa7e8db2c23a921014404bd472d20ca42e8</id>
<content type='text'>
The imsic_map_hartid_to_data() already checks hartid before using
so we don't need to check in imsic_update_hartid_table().

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Use scratch space to save per-HART PLIC pointer</title>
<updated>2023-06-05T11:20:56Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-04-19T15:59:50Z</published>
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<id>urn:sha1:b3594ac1d10ef6c7269c6381a1e826b73b06aca0</id>
<content type='text'>
Instead of using a global array indexed by hartid, we should use
scratch space to save per-HART PLIC pointer and PLIC context numbers.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Use heap in PLIC, APLIC and IMSIC drivers</title>
<updated>2023-06-05T10:27:58Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-04-19T11:25:59Z</published>
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<id>urn:sha1:30137166c67753299a7b4a4ac5e1f92269090423</id>
<content type='text'>
Let's use heap allocation in PLIC, APLIC, and IMSIC irqchip drivers
instead of using a fixed size global array.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils: Add M-mode {R/W} flags to the MMIO regions</title>
<updated>2023-01-09T12:34:28Z</updated>
<author>
<name>Himanshu Chauhan</name>
<email>hchauhan@ventanamicro.com</email>
</author>
<published>2023-01-09T05:20:42Z</published>
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<id>urn:sha1:59a08cd7d632bb2394a29956497dfe7829099997</id>
<content type='text'>
Add the M-mode readable/writable flags to mmio regions
of various drivers.

Signed-off-by: Himanshu Chauhan &lt;hchauhan@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Tested-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers</title>
<updated>2022-12-17T03:33:30Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng@tinylab.org</email>
</author>
<published>2022-12-11T06:54:24Z</published>
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<id>urn:sha1:9a2eeb4aaeac9102a7db3676035d83394784c88b</id>
<content type='text'>
Currently the context save/restore helpers writes/reads the provided
array using an index whose maximum value is determined by PLIC, which
potentially may disagree with the caller to these helpers.

Add a parameter to ask the caller to provide the size limit of the
array to ensure no out-of-bound access happens.

Signed-off-by: Bin Meng &lt;bmeng@tinylab.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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