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<title>opensbi.git/lib/utils/irqchip, branch v1.9</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/lib/utils/irqchip?h=v1.9</id>
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<updated>2026-06-10T12:43:10Z</updated>
<entry>
<title>lib: sbi_irqchip: Allow irqchip drivers advertise capabilities</title>
<updated>2026-06-10T12:43:10Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-06-08T12:52:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=8570b938444d92d4557df7e03bd9cb83fdd4c2b1'/>
<id>urn:sha1:8570b938444d92d4557df7e03bd9cb83fdd4c2b1</id>
<content type='text'>
Extend struct sbi_irqchip_device to allow irqchip drivers advertise
interrupt controller capabilities (such as wired interrupt, MSIs, etc).
This further allows other parts of OpenSBI to lookup irqchip devices
based on capabilities.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260608125257.3220114-2-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_irqchip: Allow marking hardware interrupts as reserved</title>
<updated>2026-05-12T04:25:58Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-04-23T05:23:37Z</published>
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<id>urn:sha1:d861447b0b0297db5fbe28878f8568a93fcfa965</id>
<content type='text'>
Some of the hardware interrupts may be special so allow irqchip
drivers to make these hardware interrupts as reserved. Introduce
sbi_irqchip_register_reserved() for this purpose.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260423052339.356900-5-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_irqchip: Allow interrupt client to specify line sensing</title>
<updated>2026-05-12T04:25:58Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-04-23T05:23:36Z</published>
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<id>urn:sha1:adb4caf765cc977c8de6534d0bf77df9dd243e41</id>
<content type='text'>
The interrupt client should be allowed to specify the line sensing
type of the hwirqs for which it is registering handler. To support
this, add hwirq_flags parameter to hwirq_setup() callback provided
by the irqchip driver.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260423052339.356900-4-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_irqchip: Allow registering interrupt handlers</title>
<updated>2026-03-22T05:25:58Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-02-13T05:53:42Z</published>
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<id>urn:sha1:0ab0c470d5886ce5852c94f16725c990e7f08662</id>
<content type='text'>
To handle external interrupts in M-mode, the sbi_irqchip framework
must allow registering interrupt handlers from device drivers.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260213055342.3124872-9-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_irqchip: Associate 32-bit unique ID for each irqchip device</title>
<updated>2026-03-22T05:25:08Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-02-13T05:53:41Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=e8ebd1fbc615774f0452e74c850a3dbe00b5c80d'/>
<id>urn:sha1:e8ebd1fbc615774f0452e74c850a3dbe00b5c80d</id>
<content type='text'>
Allow locating irqchip device instance using a unique 32-bit ID. This
32-bit unique ID can be set by the irqchip driver at the time of adding
irqchip device.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260213055342.3124872-8-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_irqchip: Support irqchip device targetting subset of harts</title>
<updated>2026-03-22T05:23:33Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-02-13T05:53:39Z</published>
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<id>urn:sha1:b55bb4cdcb298c12a316713d6cc7948973c14f9b</id>
<content type='text'>
It is possible to have platform where an irqchip device targets
a subset of harts and there are multiple irqchip devices to cover
all harts.

To support this scenario:
1) Add target_harts hartmask to struct sbi_irqchip_device which
   represents the set of harts targetted by the irqchip device
2) Call warm_init() and process_hwirqs() callbacks of an irqchip
   device on a hart only if irqchip device targets that particular
   hart

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260213055342.3124872-6-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Add IDC to hartindex map in struct aplic_data</title>
<updated>2026-03-22T05:22:45Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-02-13T05:53:38Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=5a300b32d546d226e55361e47d07b1c9171f07c8'/>
<id>urn:sha1:5a300b32d546d226e55361e47d07b1c9171f07c8</id>
<content type='text'>
A platform can have multiple APLICs in direct-mode targetting
different subset of harts. Add APLIC ID to hartindex map in
struct aplic_data to capture the set of harts targeted by a
given APLIC in direct-mode.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260213055342.3124872-5-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Fix context_map init in irqchip_plic_update_context_map()</title>
<updated>2026-03-22T05:22:43Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-02-13T05:53:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=6d68f3bebd206314a5b194004249524dbc0da075'/>
<id>urn:sha1:6d68f3bebd206314a5b194004249524dbc0da075</id>
<content type='text'>
The context_map[][] elements should be initialized with negative
value so that context_map does not point to anything for non-existent
PLIC contexts.

Fixes: 69448a079065 ("lib: utils/irqchip: plic: Provide a hartindex to context map")
Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260213055342.3124872-4-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_irqchip: Rename irq_handle() callback to process_hwirqs()</title>
<updated>2026-03-22T05:22:41Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-02-13T05:53:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=2110aab68fd2e33151416c1ca3070fbb79db814c'/>
<id>urn:sha1:2110aab68fd2e33151416c1ca3070fbb79db814c</id>
<content type='text'>
The irq_handle() callback of irqchip device is meant to process
hardware interrupt of the irqchip hence rename it accordingly.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260213055342.3124872-3-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: plic: context_id is signed</title>
<updated>2025-11-10T08:14:17Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2025-11-05T11:01:21Z</published>
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<id>urn:sha1:fade4399d2a47a3ff9c5ecd5dd4c3cba7a4eace7</id>
<content type='text'>
Array context_id in struct plic_data has elements of type s16.
A negative valid indicates an invalid entry.
Copying the array element to a u32 scalar hides the sign.

Use s16 as target type when copying an array element to a scalar.

Addresses-Coverity-ID: 1667176 Unsigned compared against 0
Addresses-Coverity-ID: 1667178 Logically dead code
Addresses-Coverity-ID: 1667179 Unsigned compared against 0
Addresses-Coverity-ID: 1667182 Logically dead code
Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20251105110121.47130-1-heinrich.schuchardt@canonical.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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