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<title>opensbi.git/lib/utils/serial/objects.mk, branch master</title>
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<updated>2026-02-20T11:20:35Z</updated>
<entry>
<title>lib: utils/serial: Add support for Altera JTAG UART</title>
<updated>2026-02-20T11:20:35Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>zhengxingda@iscas.ac.cn</email>
</author>
<published>2026-01-04T06:55:06Z</published>
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<id>urn:sha1:b07e449d15c534407391cb7b430117fefed084af</id>
<content type='text'>
Altera provides a JTAG UART core that provides virtual UART over JTAG
and can coexist with their virtual JTAG. [1] This core has already been
supported by Linux and the programming interface has always been stable.

Add support for it to OpenSBI to ease JTAG prototype bringing up.

The driver follows the device tree binding in mainline Linux. [2]

[1] https://docs.altera.com/r/docs/683130/25.3/embedded-peripherals-ip-user-guide/jtag-uart-core
[2] https://github.com/torvalds/linux/blob/v6.19-rc1/Documentation/devicetree/bindings/serial/altr%2Cjuart-1.0.yaml

Signed-off-by: Icenowy Zheng &lt;zhengxingda@iscas.ac.cn&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260104065506.70182-1-zhengxingda@iscas.ac.cn
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>Makefile: change to using .carray.c for carray files</title>
<updated>2024-07-04T06:41:45Z</updated>
<author>
<name>Ben Dooks</name>
<email>ben.dooks@codethink.co.uk</email>
</author>
<published>2024-07-01T14:10:59Z</published>
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<id>urn:sha1:fd9e8b17ed5017d2914f5fc7eb42ff24ff5c097b</id>
<content type='text'>
We would like to clean any files generated by the carray
scripts by just searching for the filename as the current
make system turns f.carray into f.o. Change to make the
make system turn f.carray into f.carray.o

note, command to go through .mk files changing the .o
in the .mk files is:
find . -type f -name "*.carray" | xargs -t -I fname /bin/bash -x -c ' fn=`basename -s .carray fname`; echo "$fn"; sed -i `dirname fname `/objects.mk -e s/"$fn".o/"$fn".carray.o/g'

Link: https://patchwork.ozlabs.org/project/opensbi/patch/20240401213438.590209-2-ivan.orlov0322@gmail.com/
Reported-by: Ivan Orlov &lt;ivan.orlov0322@gmail.com&gt;
Suggested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Ben Dooks &lt;ben.dooks@codethink.co.uk&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: serial: Add FDT driver for Renesas SCIF</title>
<updated>2022-12-12T13:20:35Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2022-12-10T10:30:08Z</published>
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<id>urn:sha1:0021b437377b4ea95f567f91fbf506c0b0b9e227</id>
<content type='text'>
Add FDT driver for Renesas SCIF.

    dts example:

    soc: soc {
          ....
            scif0: serial@1004b800 {
                    compatible = "renesas,scif-r9a07g043",
                                 "renesas,scif-r9a07g044";
                    reg = &lt;0 0x1004b800 0 0x400&gt;;
                    interrupts = &lt;412 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;414 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;415 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;413 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;416 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;416 IRQ_TYPE_LEVEL_HIGH&gt;;
                    interrupt-names = "eri", "rxi", "txi",
                                      "bri", "dri", "tei";
                    clocks = &lt;&amp;cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK&gt;;
                    clock-names = "fck";
                    power-domains = &lt;&amp;cpg&gt;;
                    resets = &lt;&amp;cpg R9A07G043_SCIF0_RST_SYSTEM_N&gt;;
                    status = "disabled";
            };
          ....
    };

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: serial: Add Renesas SCIF driver</title>
<updated>2022-12-12T13:20:26Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2022-12-10T10:30:07Z</published>
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<id>urn:sha1:64e8b9f72e986aba25f7cb41218b1a1088042ae3</id>
<content type='text'>
Add Renesas SCIF driver.

Based on a patch in the BSP by Takeki Hamada
&lt;takeki.hamada.ak@bp.renesas.com&gt;
Link: https://github.com/renesas-rz/rz_opensbi/commits/work/OpenSBI-PMA

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: add semihosting support</title>
<updated>2022-09-13T12:54:42Z</updated>
<author>
<name>Kautuk Consul</name>
<email>kconsul@ventanamicro.com</email>
</author>
<published>2022-09-12T10:52:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=7f09fba86e439808e0b40bdf536937c42e1ea2c9'/>
<id>urn:sha1:7f09fba86e439808e0b40bdf536937c42e1ea2c9</id>
<content type='text'>
We add RISC-V semihosting based serial console for JTAG based early
debugging.

The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Signed-off-by: Kautuk Consul &lt;kconsul@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: serial: Add Cadence UART driver</title>
<updated>2022-08-23T03:10:17Z</updated>
<author>
<name>Jun Liang Tan</name>
<email>junliang.tan@linux.starfivetech.com</email>
</author>
<published>2022-08-17T15:40:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=cbaa9b0333517b3c25bea8d1c71ac8005ff1f727'/>
<id>urn:sha1:cbaa9b0333517b3c25bea8d1c71ac8005ff1f727</id>
<content type='text'>
Add Cadence UART driver

Signed-off-by: Jun Liang Tan &lt;junliang.tan@linux.starfivetech.com&gt;
Signed-off-by: Wei Liang Lim &lt;weiliang.lim@linux.starfivetech.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: Use kconfig for enabling/disabling drivers</title>
<updated>2022-08-08T04:03:21Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-08-08T04:03:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=26bbff5f76e0ecd7a8e3f322961c481b73097a65'/>
<id>urn:sha1:26bbff5f76e0ecd7a8e3f322961c481b73097a65</id>
<content type='text'>
We update serial drivers makefile to use kconfig for enabling/disabling
drivers. To avoid compile errors, we also enable appropriate serial
drivers for each platform.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Acked-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Tested-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: Generate FDT serial driver list at compile-time</title>
<updated>2022-05-13T03:56:13Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-05-13T03:56:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=1e62705adc1268db768e4934a73242921e4550bb'/>
<id>urn:sha1:1e62705adc1268db768e4934a73242921e4550bb</id>
<content type='text'>
Instead of having FDT serial driver list hard-coded in the C source,
we generate it using carray.sh at compile-time.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils: serial: Initial commit of xlnx-uartlite</title>
<updated>2022-02-28T04:20:09Z</updated>
<author>
<name>Alistair Francis</name>
<email>alistair.francis@wdc.com</email>
</author>
<published>2022-02-24T05:01:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=4998a712b2ab504eff306110879ee05af6050177'/>
<id>urn:sha1:4998a712b2ab504eff306110879ee05af6050177</id>
<content type='text'>
Initial commit of the xlnx-uartlite device and FDT support. This was
tested by running OpenSBI on a modified QEMU virt machine using the
xlnx-uartlite for serial.

Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: Add LiteX UART support</title>
<updated>2021-11-18T07:52:02Z</updated>
<author>
<name>Gabriel Somlo</name>
<email>gsomlo@gmail.com</email>
</author>
<published>2021-11-16T19:17:04Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=52af6e4b52d0ea1d687121bfba0954c2621d2629'/>
<id>urn:sha1:52af6e4b52d0ea1d687121bfba0954c2621d2629</id>
<content type='text'>
Add support for the UART provided by the LiteX SoC
framework (https://github.com/enjoy-digital/litex),
based on its FDT info (described in the Linux tree at
Documentation/devicetree/bindings/serial/litex,liteuart.yaml).

Signed-off-by: Gabriel Somlo &lt;gsomlo@gmail.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
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