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<title>opensbi.git/lib/utils/serial/objects.mk, branch v1.2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/lib/utils/serial/objects.mk?h=v1.2</id>
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<updated>2022-12-12T13:20:35Z</updated>
<entry>
<title>lib: utils: serial: Add FDT driver for Renesas SCIF</title>
<updated>2022-12-12T13:20:35Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2022-12-10T10:30:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=0021b437377b4ea95f567f91fbf506c0b0b9e227'/>
<id>urn:sha1:0021b437377b4ea95f567f91fbf506c0b0b9e227</id>
<content type='text'>
Add FDT driver for Renesas SCIF.

    dts example:

    soc: soc {
          ....
            scif0: serial@1004b800 {
                    compatible = "renesas,scif-r9a07g043",
                                 "renesas,scif-r9a07g044";
                    reg = &lt;0 0x1004b800 0 0x400&gt;;
                    interrupts = &lt;412 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;414 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;415 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;413 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;416 IRQ_TYPE_LEVEL_HIGH&gt;,
                                 &lt;416 IRQ_TYPE_LEVEL_HIGH&gt;;
                    interrupt-names = "eri", "rxi", "txi",
                                      "bri", "dri", "tei";
                    clocks = &lt;&amp;cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK&gt;;
                    clock-names = "fck";
                    power-domains = &lt;&amp;cpg&gt;;
                    resets = &lt;&amp;cpg R9A07G043_SCIF0_RST_SYSTEM_N&gt;;
                    status = "disabled";
            };
          ....
    };

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: serial: Add Renesas SCIF driver</title>
<updated>2022-12-12T13:20:26Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2022-12-10T10:30:07Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=64e8b9f72e986aba25f7cb41218b1a1088042ae3'/>
<id>urn:sha1:64e8b9f72e986aba25f7cb41218b1a1088042ae3</id>
<content type='text'>
Add Renesas SCIF driver.

Based on a patch in the BSP by Takeki Hamada
&lt;takeki.hamada.ak@bp.renesas.com&gt;
Link: https://github.com/renesas-rz/rz_opensbi/commits/work/OpenSBI-PMA

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: add semihosting support</title>
<updated>2022-09-13T12:54:42Z</updated>
<author>
<name>Kautuk Consul</name>
<email>kconsul@ventanamicro.com</email>
</author>
<published>2022-09-12T10:52:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=7f09fba86e439808e0b40bdf536937c42e1ea2c9'/>
<id>urn:sha1:7f09fba86e439808e0b40bdf536937c42e1ea2c9</id>
<content type='text'>
We add RISC-V semihosting based serial console for JTAG based early
debugging.

The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Signed-off-by: Kautuk Consul &lt;kconsul@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: serial: Add Cadence UART driver</title>
<updated>2022-08-23T03:10:17Z</updated>
<author>
<name>Jun Liang Tan</name>
<email>junliang.tan@linux.starfivetech.com</email>
</author>
<published>2022-08-17T15:40:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=cbaa9b0333517b3c25bea8d1c71ac8005ff1f727'/>
<id>urn:sha1:cbaa9b0333517b3c25bea8d1c71ac8005ff1f727</id>
<content type='text'>
Add Cadence UART driver

Signed-off-by: Jun Liang Tan &lt;junliang.tan@linux.starfivetech.com&gt;
Signed-off-by: Wei Liang Lim &lt;weiliang.lim@linux.starfivetech.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: Use kconfig for enabling/disabling drivers</title>
<updated>2022-08-08T04:03:21Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-08-08T04:03:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=26bbff5f76e0ecd7a8e3f322961c481b73097a65'/>
<id>urn:sha1:26bbff5f76e0ecd7a8e3f322961c481b73097a65</id>
<content type='text'>
We update serial drivers makefile to use kconfig for enabling/disabling
drivers. To avoid compile errors, we also enable appropriate serial
drivers for each platform.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Acked-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Tested-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: Generate FDT serial driver list at compile-time</title>
<updated>2022-05-13T03:56:13Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-05-13T03:56:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=1e62705adc1268db768e4934a73242921e4550bb'/>
<id>urn:sha1:1e62705adc1268db768e4934a73242921e4550bb</id>
<content type='text'>
Instead of having FDT serial driver list hard-coded in the C source,
we generate it using carray.sh at compile-time.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils: serial: Initial commit of xlnx-uartlite</title>
<updated>2022-02-28T04:20:09Z</updated>
<author>
<name>Alistair Francis</name>
<email>alistair.francis@wdc.com</email>
</author>
<published>2022-02-24T05:01:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=4998a712b2ab504eff306110879ee05af6050177'/>
<id>urn:sha1:4998a712b2ab504eff306110879ee05af6050177</id>
<content type='text'>
Initial commit of the xlnx-uartlite device and FDT support. This was
tested by running OpenSBI on a modified QEMU virt machine using the
xlnx-uartlite for serial.

Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: Add LiteX UART support</title>
<updated>2021-11-18T07:52:02Z</updated>
<author>
<name>Gabriel Somlo</name>
<email>gsomlo@gmail.com</email>
</author>
<published>2021-11-16T19:17:04Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=52af6e4b52d0ea1d687121bfba0954c2621d2629'/>
<id>urn:sha1:52af6e4b52d0ea1d687121bfba0954c2621d2629</id>
<content type='text'>
Add support for the UART provided by the LiteX SoC
framework (https://github.com/enjoy-digital/litex),
based on its FDT info (described in the Linux tree at
Documentation/devicetree/bindings/serial/litex,liteuart.yaml).

Signed-off-by: Gabriel Somlo &lt;gsomlo@gmail.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: Add support for Gaisler APBUART</title>
<updated>2021-05-06T08:51:07Z</updated>
<author>
<name>Daniel Cederman</name>
<email>cederman@gaisler.com</email>
</author>
<published>2021-04-30T06:35:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=117fb6dcb147913034fe82d0ed038fa7a05f1a1d'/>
<id>urn:sha1:117fb6dcb147913034fe82d0ed038fa7a05f1a1d</id>
<content type='text'>
This patch adds support for the UART used by the NOEL-V processor.

Cobham Gaisler's NOEL-V RISC-V processor IP is available under GPL
and commercial license and is described in more detail at
https://www.gaisler.com/noelv.

Signed-off-by: Daniel Cederman &lt;cederman@gaisler.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>platform: Add support for Shakti C-class SoC from IIT-M</title>
<updated>2020-06-19T03:51:46Z</updated>
<author>
<name>Vijai Kumar K</name>
<email>vijai@behindbytes.com</email>
</author>
<published>2020-06-17T13:55:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=db56ef367cd6dc9dab94076f4c8a3fa9d91bd1f2'/>
<id>urn:sha1:db56ef367cd6dc9dab94076f4c8a3fa9d91bd1f2</id>
<content type='text'>
C-Class is a member of the SHAKTI family of processors from Indian
Institute of Technology - Madras(IIT-M).
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.

https://gitlab.com/shaktiproject/cores/c-class/blob/master/README.md

We add OpenSBI support for Shakti C-class SoC.

Signed-off-by: Vijai Kumar K &lt;vijai@behindbytes.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
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