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<title>opensbi.git/lib/utils/timer/aclint_mtimer.c, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/lib/utils/timer/aclint_mtimer.c?h=master</id>
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<updated>2025-10-28T05:58:06Z</updated>
<entry>
<title>lib: utils/timer: Expose timer update function</title>
<updated>2025-10-28T05:58:06Z</updated>
<author>
<name>Nick Hu</name>
<email>nick.hu@sifive.com</email>
</author>
<published>2025-10-20T06:34:12Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=8f8c39315520acf2c3ba2e65d5e6ed887230011a'/>
<id>urn:sha1:8f8c39315520acf2c3ba2e65d5e6ed887230011a</id>
<content type='text'>
Exposing the ACLINT timer update APIs so the user can update the mtimer
after waking up from the non-retentive suspend.

Reviewed-by: Cyan Yang &lt;cyan.yang@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Nick Hu &lt;nick.hu@sifive.com&gt;
Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-10-69a132447d8a@sifive.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_timer: Call driver warm_init from SBI core</title>
<updated>2024-11-05T11:59:13Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-09-03T04:06:49Z</published>
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<id>urn:sha1:450082874346bb25109877b7ac6a1754f089f538</id>
<content type='text'>
Currently, the platform's timer device is tracked in two places: the
core SBI implementation has `timer_dev`, and the FDT timer layer has
`current_driver`. The latter is used for warm initialization of the
timer device. However, this warm init is not specific to FDT-based
platforms; other platforms call exactly the same functions from the
same point in the boot sequence.

The code is simplified and made common across platforms by treating warm
init and exit as properties of the driver, not the platform. Then the
platform's only role is to select and prepare a driver during cold boot.

For now, only add a .warm_init hook, since none of the existing drivers
need an .exit hook. It could be added in the future if needed.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Optimize current hart scratch access</title>
<updated>2024-04-05T12:04:24Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-03-18T14:49:28Z</published>
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<id>urn:sha1:b94396c7dde699c17e81e087aadafda125f86856</id>
<content type='text'>
The address of the local scratch area is stored in each hart's mscratch
CSR. It is more efficient to read the CSR than to compute the address
from the hart ID.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: Fix sbi_hartid_to_scratch() usage in ACLINT drivers</title>
<updated>2023-07-09T05:34:57Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-07-05T06:45:15Z</published>
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<id>urn:sha1:c6a35733b74aeff612398f274ed19a74f81d1f37</id>
<content type='text'>
The cold_init() functions of ACLINT drivers should skip the HART
if sbi_hartid_to_scratch() returns NULL because we might be dealing
with a HART that is disabled in the device tree.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Use scratch space to save per-HART MTIMER pointer</title>
<updated>2023-06-05T11:16:50Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-04-19T15:57:27Z</published>
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<id>urn:sha1:f0516beae068ffce0d5a79f09a96904a661a25ba</id>
<content type='text'>
Instead of using a global array indexed by hartid, we should use
scratch space to save per-HART MTIMER pointer.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils: Add M-mode {R/W} flags to the MMIO regions</title>
<updated>2023-01-09T12:34:28Z</updated>
<author>
<name>Himanshu Chauhan</name>
<email>hchauhan@ventanamicro.com</email>
</author>
<published>2023-01-09T05:20:42Z</published>
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<id>urn:sha1:59a08cd7d632bb2394a29956497dfe7829099997</id>
<content type='text'>
Add the M-mode readable/writable flags to mmio regions
of various drivers.

Signed-off-by: Himanshu Chauhan &lt;hchauhan@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Tested-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: mtimer: add a quirk for lacking mtime register</title>
<updated>2022-12-17T05:31:03Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>uwu@icenowy.me</email>
</author>
<published>2022-12-12T08:22:37Z</published>
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<id>urn:sha1:ca7810aecdbae0630c506f05dbed641f3875ec5b</id>
<content type='text'>
T-Head developers surely have a different understanding of time CSR and
CLINT's mtime register with SiFive ones, that they did not implement
the mtime register at all -- as shown in openC906 source code, their
time CSR value is just exposed at the top of their processor IP block
and expects an external continous counter, which makes it not
overrideable, and thus mtime register is not implemented, even not for
reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
extended CSR, these systems still rely on the mtimecmp registers to
generate timer interrupts. This makes it necessary to implement T-Head
C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
reading mtime register and falls back to default code that reads time
CSR.

Add a quirk into MTIMER driver, which represents a mtime register is
lacking and time CSR value should be used instead.

Signed-off-by: Icenowy Zheng &lt;uwu@icenowy.me&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add sbi_domain_root_add_memrange() API</title>
<updated>2022-10-23T04:51:21Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2022-10-14T00:32:42Z</published>
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<id>urn:sha1:dcdaf3027489cadd513767eda6dcaa0c1ecd2d29</id>
<content type='text'>
This patch generalizes the logic to add a memory range with desired
alignment and flags of consecutive regions to the root domain.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: fix compilation when strings.h is included</title>
<updated>2022-02-04T05:34:19Z</updated>
<author>
<name>Petro Karashchenko</name>
<email>petro.karashchenko@gmail.com</email>
</author>
<published>2022-01-28T07:13:23Z</published>
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<id>urn:sha1:6ad8917b7e27e5e80fb9268492b9111b17ed2024</id>
<content type='text'>
In a systems that provide strings.h and it is included
together with sbi_bitops.h the compilation error appears.
The ffs() and fls() are provided by strings.h

Signed-off-by: Petro Karashchenko &lt;petro.karashchenko@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: fix pointer of type 'void *' used in arithmetic</title>
<updated>2022-01-21T16:28:12Z</updated>
<author>
<name>Jukka Laitinen</name>
<email>jukka.laitinen@iki.fi</email>
</author>
<published>2022-01-19T09:20:17Z</published>
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<id>urn:sha1:5d025eb2353550eadbd2fa9b8083a92fe9b07bd9</id>
<content type='text'>
Using "void *" in arithmetic causes errors with strict compiler settings:
"error: pointer of type 'void *' used in arithmetic [-Werror=pointer-arith]"

Avoid these by calculating on "char *" where 1-byte data size is assumed.

Signed-off-by: Jukka Laitinen &lt;jukkax@ssrc.tii.ae&gt;
Reviewed-by: Dong Du &lt;Dd_nirvana@sjtu.edu.cn&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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