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<title>opensbi.git/lib/utils/timer/aclint_mtimer.c, branch v1.2</title>
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<updated>2022-12-17T05:31:03Z</updated>
<entry>
<title>lib: utils/timer: mtimer: add a quirk for lacking mtime register</title>
<updated>2022-12-17T05:31:03Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>uwu@icenowy.me</email>
</author>
<published>2022-12-12T08:22:37Z</published>
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<id>urn:sha1:ca7810aecdbae0630c506f05dbed641f3875ec5b</id>
<content type='text'>
T-Head developers surely have a different understanding of time CSR and
CLINT's mtime register with SiFive ones, that they did not implement
the mtime register at all -- as shown in openC906 source code, their
time CSR value is just exposed at the top of their processor IP block
and expects an external continous counter, which makes it not
overrideable, and thus mtime register is not implemented, even not for
reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
extended CSR, these systems still rely on the mtimecmp registers to
generate timer interrupts. This makes it necessary to implement T-Head
C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
reading mtime register and falls back to default code that reads time
CSR.

Add a quirk into MTIMER driver, which represents a mtime register is
lacking and time CSR value should be used instead.

Signed-off-by: Icenowy Zheng &lt;uwu@icenowy.me&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add sbi_domain_root_add_memrange() API</title>
<updated>2022-10-23T04:51:21Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2022-10-14T00:32:42Z</published>
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<id>urn:sha1:dcdaf3027489cadd513767eda6dcaa0c1ecd2d29</id>
<content type='text'>
This patch generalizes the logic to add a memory range with desired
alignment and flags of consecutive regions to the root domain.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: fix compilation when strings.h is included</title>
<updated>2022-02-04T05:34:19Z</updated>
<author>
<name>Petro Karashchenko</name>
<email>petro.karashchenko@gmail.com</email>
</author>
<published>2022-01-28T07:13:23Z</published>
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<id>urn:sha1:6ad8917b7e27e5e80fb9268492b9111b17ed2024</id>
<content type='text'>
In a systems that provide strings.h and it is included
together with sbi_bitops.h the compilation error appears.
The ffs() and fls() are provided by strings.h

Signed-off-by: Petro Karashchenko &lt;petro.karashchenko@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: fix pointer of type 'void *' used in arithmetic</title>
<updated>2022-01-21T16:28:12Z</updated>
<author>
<name>Jukka Laitinen</name>
<email>jukka.laitinen@iki.fi</email>
</author>
<published>2022-01-19T09:20:17Z</published>
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<id>urn:sha1:5d025eb2353550eadbd2fa9b8083a92fe9b07bd9</id>
<content type='text'>
Using "void *" in arithmetic causes errors with strict compiler settings:
"error: pointer of type 'void *' used in arithmetic [-Werror=pointer-arith]"

Avoid these by calculating on "char *" where 1-byte data size is assumed.

Signed-off-by: Jukka Laitinen &lt;jukkax@ssrc.tii.ae&gt;
Reviewed-by: Dong Du &lt;Dd_nirvana@sjtu.edu.cn&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add timer frequency to struct sbi_timer_device</title>
<updated>2021-09-26T14:22:10Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2021-09-14T16:21:48Z</published>
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<id>urn:sha1:12e7af9ab7ef9adf61b9138e2c38e3aeef3c140b</id>
<content type='text'>
Generic mdelay() and udelay() functions can be provided by the
sbi_timer framework if timer frequency is available in the timer
instance provided by the platform support or timer driver.

This patch adds timer frequency (timer_freq) member in the
struct sbi_timer_device for above purpose.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Simplify MTIMER synchronization</title>
<updated>2021-08-14T03:37:42Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2021-07-24T05:05:01Z</published>
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<id>urn:sha1:7aa6c9aa96049b741b754b7340ea96a37719de27</id>
<content type='text'>
We simplify MTIMER synchronization as follows:

1) Detect MTIMER devices with unique (or non-shared) MTIME
   register at boot-time
2) Select first MTIMER device with no associated HART as our
   reference MTIMER device
3) Only synchronize MTIMER devices with unique (or non-shared)
   MTIME register using reference MTIMER device
4) Directly update the MTIME register at time of synchronization
   because MTIME is a read/write register.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Allow separate base addresses for MTIME and MTIMECMP</title>
<updated>2021-08-14T03:32:33Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2021-07-23T08:39:43Z</published>
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<id>urn:sha1:e0d1b9db8abd8288afbaa4f93a4ace6a9b6f0100</id>
<content type='text'>
We extend the ACLINT library to support separate base addresses
for MTIME and MTIMECMP registers.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Add ACLINT MTIMER library</title>
<updated>2021-06-24T04:08:47Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2021-05-20T05:31:57Z</published>
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<id>urn:sha1:4519e29c51315205119ce03ff0e5152def647ed5</id>
<content type='text'>
We add common ACLINT MTIMER library similar to the CLINT library
so that OpenSBI platforms can use it.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
</content>
</entry>
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