Unnamed repository; edit this file 'description' to name the repository. http://cgit.235523.xyz/opensbi.git/atom/lib/utils/timer/andes_plmt.c?h=v1.5 2023-10-06T11:23:26Z 2023-10-06T11:23:26Z Yu Chien Peter Lin peterlin@andestech.com 2023-09-27T10:08:31Z urn:sha1:d36709fcafe2d39c3d999489a8ca836b138e4f04 This patch adds unspecified permission flags for the PLICSW region and updates the permission of the PLMT region. With this update, both regions will become M-mode only read/write regions in the root domain. Domain0 Region00: 0x00000000f0300000-0x00000000f0300fff M: (I,R,W) S/U: (R,W) Domain0 Region01: 0x0000000000040000-0x000000000005ffff M: (R,W) S/U: () Domain0 Region02: 0x0000000000000000-0x000000000003ffff M: (R,X) S/U: () > Domain0 Region03: 0x00000000e6000000-0x00000000e60fffff M: (I,R,W) S/U: () > Domain0 Region04: 0x00000000e6400000-0x00000000e67fffff M: (I,R,W) S/U: () Domain0 Region05: 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) The PMP rules of AE350-AX65 (single-core) w/ Smepmp: p/x $pmpcfg0 $1 = {0x1f9b9b9d9b1e00, pmp0cfg = {0x0}, L--AAXWR pmp1cfg = {0x1e} (00011110), pmpaddr1: 0xf0300000 ~ 0xf0300fff (UART1) pmp2cfg = {0x9b} (10011011), pmpaddr2: 0x40000 ~ 0x5ffff pmp3cfg = {0x9d} (10011101), pmpaddr3: 0x0 ~ 0x3ffff pmp4cfg = {0x9b} (10011011), pmpaddr4: 0xe6000000 ~ 0xe60fffff (PLMT) pmp5cfg = {0x9b} (10011011), pmpaddr5: 0xe6400000 ~ 0xe67fffff (PLICSW) pmp6cfg = {0x1f} (00011111), pmpaddr6: 0x0 ~ 0xffffffffff pmp7cfg = {0x0 }} The PMP rules of AE350-AX45MP (qual-core) w/o Smepmp: p/x $pmpcfg0 $1 = {0x1f181818181b, L--AAXWR pmp0cfg = {0x1b}, (00011011), pmpaddr0: 0xf0300000 ~ 0xf0300fff (UART1) pmp1cfg = {0x18}, (00011000), pmpaddr1: 0x40000 ~ 0x5ffff pmp2cfg = {0x18}, (00011000), pmpaddr2: 0x0 ~ 0x3ffff pmp3cfg = {0x18}, (00011000), pmpaddr3: 0xe6000000 ~ 0xe60fffff (PLMT) pmp4cfg = {0x18}, (00011000), pmpaddr4: 0xe6400000 ~ 0xe67fffff (PLICSW) pmp5cfg = {0x1f}, (00011111), pmpaddr5: 0x0 ~ 0x1ffffffff pmp6cfg = {0x0 }} Note that starting from this patch, we restrict the S/U-mode read permission to the PLMT region, since we should read the TIME CSR in a lower privilege mode. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> 2022-10-23T04:56:39Z Yu Chien Peter Lin peterlin@andestech.com 2022-10-14T00:32:46Z urn:sha1:ef9f02e7fba47412d6c057ba78fd3d89cb4e5fc3 Since we can get the PLMT base address and timer frequency from device tree, move plmt timer device to fdt timer framework. dts example (Quad-core AX45MP): cpus { ... timebase-frequency = <0x3938700>; ... } soc { ... plmt0@e6000000 { compatible = "andestech,plmt0"; reg = <0x00 0xe6000000 0x00 0x100000>; interrupts-extended = <&cpu0_intc 0x07 &cpu1_intc 0x07 &cpu2_intc 0x07 &cpu3_intc 0x07>; }; ... } Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org>