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<title>opensbi.git/lib/utils/timer/fdt_timer_mtimer.c, branch v1.4</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/lib/utils/timer/fdt_timer_mtimer.c?h=v1.4</id>
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<updated>2023-12-27T06:27:33Z</updated>
<entry>
<title>lib: utils/timer: mtimer: only use regname for aclint</title>
<updated>2023-12-27T06:27:33Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-12-27T00:46:11Z</published>
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<id>urn:sha1:ba29293dc947e13fa2e63de7ed289d7bb9b540f4</id>
<content type='text'>
The parser will fail if the timer is clint timer and has regname
property. As the regname is only meaningful for aclint, it is more
robust to only check regname for aclint timer.

Fixes: 6112d58 ("lib: utils/fdt: Allow to use reg-names when parsing ACLINT")
Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: mtimer: add separate T-Head C9xx CLINT mtimer compatible</title>
<updated>2023-11-16T11:23:48Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-11-16T09:07:14Z</published>
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<id>urn:sha1:accafb13d47ca1511364def6cd8840ef1f947e50</id>
<content type='text'>
T-HEAD allows soc vendor to map the mtimer and mswi of C9xx clint on
different address, which may cause a misuse if use the same compatible
string, add a new timer compatible string to avoid this.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Link: https://lore.kernel.org/linux-riscv/6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang@outlook.com/
Reviewed-by: Guo Ren &lt;guoren@kernel.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Allow ACLINT MTIMER driver to setup quirks</title>
<updated>2023-11-16T11:20:42Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-11-16T09:07:13Z</published>
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<id>urn:sha1:896d2c99e239c8142be16cc6df979e7f805d8896</id>
<content type='text'>
The quirks checking will cause ACLINT step into a CLINT code path, this
is not expected when ACLINT needs custom quirks.

Add a new quirk to identify custom ACLINT, and apply the general quirks
after applying CLINT specific quirks.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Use heap in ACLINT MTIMER driver</title>
<updated>2023-06-05T10:28:42Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-04-19T11:43:22Z</published>
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<id>urn:sha1:7e5636ac3788451991a65791c5adcc7798dcc22a</id>
<content type='text'>
Let's use heap allocation in ACLINT MTIMER driver instead of using
a fixed size global array.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible</title>
<updated>2022-12-17T05:31:06Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>uwu@icenowy.me</email>
</author>
<published>2022-12-12T08:22:38Z</published>
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<id>urn:sha1:b848d8763a737de44b64bfc036c8f51200226440</id>
<content type='text'>
As we already added the quirk for lacking mtime register to MTIMER
driver, add T-Head C9xx CLINT compatible to it and wire the quirk.

Signed-off-by: Icenowy Zheng &lt;uwu@icenowy.me&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: mtimer: add a quirk for lacking mtime register</title>
<updated>2022-12-17T05:31:03Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>uwu@icenowy.me</email>
</author>
<published>2022-12-12T08:22:37Z</published>
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<id>urn:sha1:ca7810aecdbae0630c506f05dbed641f3875ec5b</id>
<content type='text'>
T-Head developers surely have a different understanding of time CSR and
CLINT's mtime register with SiFive ones, that they did not implement
the mtime register at all -- as shown in openC906 source code, their
time CSR value is just exposed at the top of their processor IP block
and expects an external continous counter, which makes it not
overrideable, and thus mtime register is not implemented, even not for
reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
extended CSR, these systems still rely on the mtimecmp registers to
generate timer interrupts. This makes it necessary to implement T-Head
C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
reading mtime register and falls back to default code that reads time
CSR.

Add a quirk into MTIMER driver, which represents a mtime register is
lacking and time CSR value should be used instead.

Signed-off-by: Icenowy Zheng &lt;uwu@icenowy.me&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Remove Allwinner D1 CLINT compatibles</title>
<updated>2022-06-22T05:25:37Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2022-06-22T04:57:42Z</published>
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<id>urn:sha1:6f1fe98c2f565a394f258178b0daa3843672395c</id>
<content type='text'>
The allwinner,sun20i-d1-clint compatible string is not documented in any
official binding, so it should not be used by drivers.

The MSWI in the D1 CLINT is compatible with the ACLINT specification, so
it can take advantage of generic driver support. However, that is only
possible if the MSWI and MTIMER are split into separate DT nodes. This
means the final binding for this device is likely to be incompatible
with what is implemented here.

Remove this compatible string from the driver to prevent it from
appearing in a stable version and causing future issues.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Add a separate compatible for the D1 CLINT</title>
<updated>2022-06-21T03:50:59Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2021-10-20T01:58:38Z</published>
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<id>urn:sha1:7738345396fbbae543a5af14fbc965d9163c12a0</id>
<content type='text'>
The CLINT in the Allwinner D1 SoC apparently does not support 64-bit
MMIO access. A property was added to support this quirk (and that
property was copied to the ACLINT MTIMER code). However, since this
difference in behavior makes the D1 CLINT incompatible with the SiFive
CLINT's programming interface, a better solution is to use a separate
compatible string.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/fdt: Require match data to be const</title>
<updated>2022-05-30T05:02:35Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2022-05-29T18:32:11Z</published>
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<id>urn:sha1:fab0379bb60d6e177018b53f07718b69ba34948d</id>
<content type='text'>
Match data stores hardware attributes which do not change at runtime, so
it does not need to be mutable. Make it const.

Reviewed-by: Guo Ren &lt;guoren@kernel.org&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add timer frequency to struct sbi_timer_device</title>
<updated>2021-09-26T14:22:10Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2021-09-14T16:21:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=12e7af9ab7ef9adf61b9138e2c38e3aeef3c140b'/>
<id>urn:sha1:12e7af9ab7ef9adf61b9138e2c38e3aeef3c140b</id>
<content type='text'>
Generic mdelay() and udelay() functions can be provided by the
sbi_timer framework if timer frequency is available in the timer
instance provided by the platform support or timer driver.

This patch adds timer frequency (timer_freq) member in the
struct sbi_timer_device for above purpose.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
</content>
</entry>
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