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<title>opensbi.git/lib/utils/timer/fdt_timer_mtimer.c, branch v1.6</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/lib/utils/timer/fdt_timer_mtimer.c?h=v1.6</id>
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<updated>2024-11-28T12:27:20Z</updated>
<entry>
<title>lib: utils/timer: Use fdt_driver for initialization</title>
<updated>2024-11-28T12:27:20Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-11T22:02:55Z</published>
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<id>urn:sha1:a387a8dff05bd433c686b77dab13bab0221710e5</id>
<content type='text'>
The timer driver subsystem does not need any extra data, so it can use
`struct fdt_driver` directly. The generic fdt_timer_init() performs a
best-effort initialization of all matching DT nodes.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: Drop timer warm init and exit hooks</title>
<updated>2024-11-05T12:09:31Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-09-03T04:06:50Z</published>
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<id>urn:sha1:99b01ab610acf6ff7c3d0199f13f5b41322a22e2</id>
<content type='text'>
Now that driver lifecycle is managed from within the SBI timer core,
platforms need only to initialize the driver once during cold init.
Remove the remaining platform hooks that are no longer used.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_timer: Call driver warm_init from SBI core</title>
<updated>2024-11-05T11:59:13Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-09-03T04:06:49Z</published>
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<id>urn:sha1:450082874346bb25109877b7ac6a1754f089f538</id>
<content type='text'>
Currently, the platform's timer device is tracked in two places: the
core SBI implementation has `timer_dev`, and the FDT timer layer has
`current_driver`. The latter is used for warm initialization of the
timer device. However, this warm init is not specific to FDT-based
platforms; other platforms call exactly the same functions from the
same point in the boot sequence.

The code is simplified and made common across platforms by treating warm
init and exit as properties of the driver, not the platform. Then the
platform's only role is to select and prepare a driver during cold boot.

For now, only add a .warm_init hook, since none of the existing drivers
need an .exit hook. It could be added in the future if needed.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Constify FDT pointers in parsing functions</title>
<updated>2024-08-24T07:32:48Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-07-31T04:58:52Z</published>
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<id>urn:sha1:b15cc7715a02b269b7789159401d428c20e23c03</id>
<content type='text'>
Indicate that none of these functions modify the devicetree by
constifying the parameter type.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: mtimer: only use regname for aclint</title>
<updated>2023-12-27T06:27:33Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-12-27T00:46:11Z</published>
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<id>urn:sha1:ba29293dc947e13fa2e63de7ed289d7bb9b540f4</id>
<content type='text'>
The parser will fail if the timer is clint timer and has regname
property. As the regname is only meaningful for aclint, it is more
robust to only check regname for aclint timer.

Fixes: 6112d58 ("lib: utils/fdt: Allow to use reg-names when parsing ACLINT")
Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: mtimer: add separate T-Head C9xx CLINT mtimer compatible</title>
<updated>2023-11-16T11:23:48Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-11-16T09:07:14Z</published>
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<id>urn:sha1:accafb13d47ca1511364def6cd8840ef1f947e50</id>
<content type='text'>
T-HEAD allows soc vendor to map the mtimer and mswi of C9xx clint on
different address, which may cause a misuse if use the same compatible
string, add a new timer compatible string to avoid this.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Link: https://lore.kernel.org/linux-riscv/6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang@outlook.com/
Reviewed-by: Guo Ren &lt;guoren@kernel.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Allow ACLINT MTIMER driver to setup quirks</title>
<updated>2023-11-16T11:20:42Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-11-16T09:07:13Z</published>
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<id>urn:sha1:896d2c99e239c8142be16cc6df979e7f805d8896</id>
<content type='text'>
The quirks checking will cause ACLINT step into a CLINT code path, this
is not expected when ACLINT needs custom quirks.

Add a new quirk to identify custom ACLINT, and apply the general quirks
after applying CLINT specific quirks.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Use heap in ACLINT MTIMER driver</title>
<updated>2023-06-05T10:28:42Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-04-19T11:43:22Z</published>
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<id>urn:sha1:7e5636ac3788451991a65791c5adcc7798dcc22a</id>
<content type='text'>
Let's use heap allocation in ACLINT MTIMER driver instead of using
a fixed size global array.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible</title>
<updated>2022-12-17T05:31:06Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>uwu@icenowy.me</email>
</author>
<published>2022-12-12T08:22:38Z</published>
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<id>urn:sha1:b848d8763a737de44b64bfc036c8f51200226440</id>
<content type='text'>
As we already added the quirk for lacking mtime register to MTIMER
driver, add T-Head C9xx CLINT compatible to it and wire the quirk.

Signed-off-by: Icenowy Zheng &lt;uwu@icenowy.me&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: mtimer: add a quirk for lacking mtime register</title>
<updated>2022-12-17T05:31:03Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>uwu@icenowy.me</email>
</author>
<published>2022-12-12T08:22:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=ca7810aecdbae0630c506f05dbed641f3875ec5b'/>
<id>urn:sha1:ca7810aecdbae0630c506f05dbed641f3875ec5b</id>
<content type='text'>
T-Head developers surely have a different understanding of time CSR and
CLINT's mtime register with SiFive ones, that they did not implement
the mtime register at all -- as shown in openC906 source code, their
time CSR value is just exposed at the top of their processor IP block
and expects an external continous counter, which makes it not
overrideable, and thus mtime register is not implemented, even not for
reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
extended CSR, these systems still rely on the mtimecmp registers to
generate timer interrupts. This makes it necessary to implement T-Head
C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
reading mtime register and falls back to default code that reads time
CSR.

Add a quirk into MTIMER driver, which represents a mtime register is
lacking and time CSR value should be used instead.

Signed-off-by: Icenowy Zheng &lt;uwu@icenowy.me&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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