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<title>opensbi.git/lib/utils/timer, branch v1.2</title>
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<id>http://cgit.235523.xyz/opensbi.git/atom/lib/utils/timer?h=v1.2</id>
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<updated>2022-12-17T05:31:06Z</updated>
<entry>
<title>lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible</title>
<updated>2022-12-17T05:31:06Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>uwu@icenowy.me</email>
</author>
<published>2022-12-12T08:22:38Z</published>
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<id>urn:sha1:b848d8763a737de44b64bfc036c8f51200226440</id>
<content type='text'>
As we already added the quirk for lacking mtime register to MTIMER
driver, add T-Head C9xx CLINT compatible to it and wire the quirk.

Signed-off-by: Icenowy Zheng &lt;uwu@icenowy.me&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: mtimer: add a quirk for lacking mtime register</title>
<updated>2022-12-17T05:31:03Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>uwu@icenowy.me</email>
</author>
<published>2022-12-12T08:22:37Z</published>
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<id>urn:sha1:ca7810aecdbae0630c506f05dbed641f3875ec5b</id>
<content type='text'>
T-Head developers surely have a different understanding of time CSR and
CLINT's mtime register with SiFive ones, that they did not implement
the mtime register at all -- as shown in openC906 source code, their
time CSR value is just exposed at the top of their processor IP block
and expects an external continous counter, which makes it not
overrideable, and thus mtime register is not implemented, even not for
reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
extended CSR, these systems still rely on the mtimecmp registers to
generate timer interrupts. This makes it necessary to implement T-Head
C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
reading mtime register and falls back to default code that reads time
CSR.

Add a quirk into MTIMER driver, which represents a mtime register is
lacking and time CSR value should be used instead.

Signed-off-by: Icenowy Zheng &lt;uwu@icenowy.me&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Add Andes fdt timer support</title>
<updated>2022-10-23T04:56:39Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2022-10-14T00:32:46Z</published>
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<id>urn:sha1:ef9f02e7fba47412d6c057ba78fd3d89cb4e5fc3</id>
<content type='text'>
Since we can get the PLMT base address and timer frequency from
device tree, move plmt timer device to fdt timer framework.

dts example (Quad-core AX45MP):

  cpus {
      ...
      timebase-frequency = &lt;0x3938700&gt;;
      ...
  }
  soc {
      ...
      plmt0@e6000000 {
          compatible = "andestech,plmt0";
          reg = &lt;0x00 0xe6000000 0x00 0x100000&gt;;
          interrupts-extended = &lt;&amp;cpu0_intc 0x07
                                 &amp;cpu1_intc 0x07
                                 &amp;cpu2_intc 0x07
                                 &amp;cpu3_intc 0x07&gt;;
      };
      ...
  }

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add sbi_domain_root_add_memrange() API</title>
<updated>2022-10-23T04:51:21Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2022-10-14T00:32:42Z</published>
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<id>urn:sha1:dcdaf3027489cadd513767eda6dcaa0c1ecd2d29</id>
<content type='text'>
This patch generalizes the logic to add a memory range with desired
alignment and flags of consecutive regions to the root domain.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/fdt: Use kconfig for enabling/disabling</title>
<updated>2022-08-08T04:04:08Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-08-08T04:04:08Z</published>
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<id>urn:sha1:68d7b85ec75119787d7c672062de5d29156c44be</id>
<content type='text'>
We update FDT support makefile to use kconfig for enabling/disabling.
To avoid compilation errors, we also enable FDT for each platform.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Acked-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Tested-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Use kconfig for enabling/disabling drivers</title>
<updated>2022-08-08T04:03:37Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-08-08T04:03:37Z</published>
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<id>urn:sha1:013dbb3a60db0f7d9c92990b266c3df9d3552c0c</id>
<content type='text'>
We update timer drivers makefile to use kconfig for enabling/disabling
drivers. To avoid compile errors, we also enable appropriate timer
drivers for each platform.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Acked-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Tested-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Remove Allwinner D1 CLINT compatibles</title>
<updated>2022-06-22T05:25:37Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2022-06-22T04:57:42Z</published>
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<id>urn:sha1:6f1fe98c2f565a394f258178b0daa3843672395c</id>
<content type='text'>
The allwinner,sun20i-d1-clint compatible string is not documented in any
official binding, so it should not be used by drivers.

The MSWI in the D1 CLINT is compatible with the ACLINT specification, so
it can take advantage of generic driver support. However, that is only
possible if the MSWI and MTIMER are split into separate DT nodes. This
means the final binding for this device is likely to be incompatible
with what is implemented here.

Remove this compatible string from the driver to prevent it from
appearing in a stable version and causing future issues.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Add a separate compatible for the D1 CLINT</title>
<updated>2022-06-21T03:50:59Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2021-10-20T01:58:38Z</published>
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<id>urn:sha1:7738345396fbbae543a5af14fbc965d9163c12a0</id>
<content type='text'>
The CLINT in the Allwinner D1 SoC apparently does not support 64-bit
MMIO access. A property was added to support this quirk (and that
property was copied to the ACLINT MTIMER code). However, since this
difference in behavior makes the D1 CLINT incompatible with the SiFive
CLINT's programming interface, a better solution is to use a separate
compatible string.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/fdt: Require match data to be const</title>
<updated>2022-05-30T05:02:35Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2022-05-29T18:32:11Z</published>
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<id>urn:sha1:fab0379bb60d6e177018b53f07718b69ba34948d</id>
<content type='text'>
Match data stores hardware attributes which do not change at runtime, so
it does not need to be mutable. Make it const.

Reviewed-by: Guo Ren &lt;guoren@kernel.org&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Generate FDT timer driver list at compile-time</title>
<updated>2022-05-13T03:56:20Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-05-13T03:56:20Z</published>
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<id>urn:sha1:bfeb305e0f8da3f8bdff97a21a6628c3156fbfff</id>
<content type='text'>
Instead of having FDT timer driver list hard-coded in the C source,
we generate it using carray.sh at compile-time.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
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