opensbi.git/lib/utils/timer, branch v1.3

lib: utils/timer: Use scratch space to save per-HART MTIMER pointer

2023-06-05T11:16:50Z

Instead of using a global array indexed by hartid, we should use scratch space to save per-HART MTIMER pointer. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones

lib: utils/timer: Use heap in ACLINT MTIMER driver

2023-06-05T10:28:42Z

Let's use heap allocation in ACLINT MTIMER driver instead of using a fixed size global array. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones

lib: utils: Improve fdt_timer

2023-05-26T07:17:22Z

Remove dummy driver. Optimize fdt_timer_cold_init to exit the loop early. Signed-off-by: Xiang W Reviewed-by: Anup Patel

lib: utils: Add M-mode {R/W} flags to the MMIO regions

2023-01-09T12:34:28Z

Add the M-mode readable/writable flags to mmio regions of various drivers. Signed-off-by: Himanshu Chauhan Reviewed-by: Anup Patel Tested-by: Anup Patel

lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible

2022-12-17T05:31:06Z

As we already added the quirk for lacking mtime register to MTIMER driver, add T-Head C9xx CLINT compatible to it and wire the quirk. Signed-off-by: Icenowy Zheng Reviewed-by: Anup Patel

lib: utils/timer: mtimer: add a quirk for lacking mtime register

2022-12-17T05:31:03Z

T-Head developers surely have a different understanding of time CSR and CLINT's mtime register with SiFive ones, that they did not implement the mtime register at all -- as shown in openC906 source code, their time CSR value is just exposed at the top of their processor IP block and expects an external continous counter, which makes it not overrideable, and thus mtime register is not implemented, even not for reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS extended CSR, these systems still rely on the mtimecmp registers to generate timer interrupts. This makes it necessary to implement T-Head C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing reading mtime register and falls back to default code that reads time CSR. Add a quirk into MTIMER driver, which represents a mtime register is lacking and time CSR value should be used instead. Signed-off-by: Icenowy Zheng Reviewed-by: Anup Patel

lib: utils/timer: Add Andes fdt timer support

2022-10-23T04:56:39Z

Since we can get the PLMT base address and timer frequency from device tree, move plmt timer device to fdt timer framework. dts example (Quad-core AX45MP): cpus { ... timebase-frequency = <0x3938700>; ... } soc { ... plmt0@e6000000 { compatible = "andestech,plmt0"; reg = <0x00 0xe6000000 0x00 0x100000>; interrupts-extended = <&cpu0_intc 0x07 &cpu1_intc 0x07 &cpu2_intc 0x07 &cpu3_intc 0x07>; }; ... } Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

lib: sbi: Add sbi_domain_root_add_memrange() API

2022-10-23T04:51:21Z

This patch generalizes the logic to add a memory range with desired alignment and flags of consecutive regions to the root domain. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

lib: utils/fdt: Use kconfig for enabling/disabling

2022-08-08T04:04:08Z

We update FDT support makefile to use kconfig for enabling/disabling. To avoid compilation errors, we also enable FDT for each platform. Signed-off-by: Anup Patel Tested-by: Andrew Jones Acked-by: Atish Patra Tested-by: Atish Patra

lib: utils/timer: Use kconfig for enabling/disabling drivers

2022-08-08T04:03:37Z

We update timer drivers makefile to use kconfig for enabling/disabling drivers. To avoid compile errors, we also enable appropriate timer drivers for each platform. Signed-off-by: Anup Patel Tested-by: Andrew Jones Acked-by: Atish Patra Tested-by: Atish Patra