<feed xmlns='http://www.w3.org/2005/Atom'>
<title>opensbi.git/lib/utils/timer, branch v1.5</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/opensbi.git/atom/lib/utils/timer?h=v1.5</id>
<link rel='self' href='http://cgit.235523.xyz/opensbi.git/atom/lib/utils/timer?h=v1.5'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/'/>
<updated>2024-06-13T13:01:40Z</updated>
<entry>
<title>lib: utils/timer: Skip initialize timer when dt is not enabled</title>
<updated>2024-06-13T13:01:40Z</updated>
<author>
<name>Xiang W</name>
<email>wxjstz@126.com</email>
</author>
<published>2024-06-11T11:19:29Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=5e3ad7d577573e158bb2ca90ae647d64db3f4a32'/>
<id>urn:sha1:5e3ad7d577573e158bb2ca90ae647d64db3f4a32</id>
<content type='text'>
When the dt node has a status property and the value is not ok or
okay, skip initializing timer.

Signed-off-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Optimize current hart scratch access</title>
<updated>2024-04-05T12:04:24Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-03-18T14:49:28Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=b94396c7dde699c17e81e087aadafda125f86856'/>
<id>urn:sha1:b94396c7dde699c17e81e087aadafda125f86856</id>
<content type='text'>
The address of the local scratch area is stored in each hart's mscratch
CSR. It is more efficient to read the CSR than to compute the address
from the hart ID.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: mtimer: only use regname for aclint</title>
<updated>2023-12-27T06:27:33Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-12-27T00:46:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=ba29293dc947e13fa2e63de7ed289d7bb9b540f4'/>
<id>urn:sha1:ba29293dc947e13fa2e63de7ed289d7bb9b540f4</id>
<content type='text'>
The parser will fail if the timer is clint timer and has regname
property. As the regname is only meaningful for aclint, it is more
robust to only check regname for aclint timer.

Fixes: 6112d58 ("lib: utils/fdt: Allow to use reg-names when parsing ACLINT")
Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: mtimer: add separate T-Head C9xx CLINT mtimer compatible</title>
<updated>2023-11-16T11:23:48Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-11-16T09:07:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=accafb13d47ca1511364def6cd8840ef1f947e50'/>
<id>urn:sha1:accafb13d47ca1511364def6cd8840ef1f947e50</id>
<content type='text'>
T-HEAD allows soc vendor to map the mtimer and mswi of C9xx clint on
different address, which may cause a misuse if use the same compatible
string, add a new timer compatible string to avoid this.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Link: https://lore.kernel.org/linux-riscv/6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang@outlook.com/
Reviewed-by: Guo Ren &lt;guoren@kernel.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Allow ACLINT MTIMER driver to setup quirks</title>
<updated>2023-11-16T11:20:42Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@outlook.com</email>
</author>
<published>2023-11-16T09:07:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=896d2c99e239c8142be16cc6df979e7f805d8896'/>
<id>urn:sha1:896d2c99e239c8142be16cc6df979e7f805d8896</id>
<content type='text'>
The quirks checking will cause ACLINT step into a CLINT code path, this
is not expected when ACLINT needs custom quirks.

Add a new quirk to identify custom ACLINT, and apply the general quirks
after applying CLINT specific quirks.

Signed-off-by: Inochi Amaoto &lt;inochiama@outlook.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: timer/ipi: Update memregion flags for PLMT and PLICSW</title>
<updated>2023-10-06T11:23:26Z</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2023-09-27T10:08:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=d36709fcafe2d39c3d999489a8ca836b138e4f04'/>
<id>urn:sha1:d36709fcafe2d39c3d999489a8ca836b138e4f04</id>
<content type='text'>
This patch adds unspecified permission flags for the PLICSW region
and updates the permission of the PLMT region.

With this update, both regions will become M-mode only read/write
regions in the root domain.

  Domain0 Region00: 0x00000000f0300000-0x00000000f0300fff M: (I,R,W) S/U: (R,W)
  Domain0 Region01: 0x0000000000040000-0x000000000005ffff M: (R,W) S/U: ()
  Domain0 Region02: 0x0000000000000000-0x000000000003ffff M: (R,X) S/U: ()
&gt; Domain0 Region03: 0x00000000e6000000-0x00000000e60fffff M: (I,R,W) S/U: ()
&gt; Domain0 Region04: 0x00000000e6400000-0x00000000e67fffff M: (I,R,W) S/U: ()
  Domain0 Region05: 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X)

The PMP rules of AE350-AX65 (single-core) w/ Smepmp:

  p/x $pmpcfg0
  $1 = {0x1f9b9b9d9b1e00,
  pmp0cfg = {0x0},
                    L--AAXWR
  pmp1cfg = {0x1e} (00011110), pmpaddr1: 0xf0300000 ~   0xf0300fff  (UART1)
  pmp2cfg = {0x9b} (10011011), pmpaddr2:    0x40000 ~      0x5ffff
  pmp3cfg = {0x9d} (10011101), pmpaddr3:        0x0 ~      0x3ffff
  pmp4cfg = {0x9b} (10011011), pmpaddr4: 0xe6000000 ~   0xe60fffff  (PLMT)
  pmp5cfg = {0x9b} (10011011), pmpaddr5: 0xe6400000 ~   0xe67fffff  (PLICSW)
  pmp6cfg = {0x1f} (00011111), pmpaddr6:        0x0 ~ 0xffffffffff
  pmp7cfg = {0x0 }}

The PMP rules of AE350-AX45MP (qual-core) w/o Smepmp:

  p/x $pmpcfg0
  $1 = {0x1f181818181b,
                     L--AAXWR
  pmp0cfg = {0x1b}, (00011011), pmpaddr0: 0xf0300000 ~  0xf0300fff  (UART1)
  pmp1cfg = {0x18}, (00011000), pmpaddr1:    0x40000 ~     0x5ffff
  pmp2cfg = {0x18}, (00011000), pmpaddr2:        0x0 ~     0x3ffff
  pmp3cfg = {0x18}, (00011000), pmpaddr3: 0xe6000000 ~  0xe60fffff  (PLMT)
  pmp4cfg = {0x18}, (00011000), pmpaddr4: 0xe6400000 ~  0xe67fffff  (PLICSW)
  pmp5cfg = {0x1f}, (00011111), pmpaddr5:        0x0 ~ 0x1ffffffff
  pmp6cfg = {0x0 }}

Note that starting from this patch, we restrict the S/U-mode read
permission to the PLMT region, since we should read the TIME CSR
in a lower privilege mode.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: Fix sbi_hartid_to_scratch() usage in ACLINT drivers</title>
<updated>2023-07-09T05:34:57Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-07-05T06:45:15Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=c6a35733b74aeff612398f274ed19a74f81d1f37'/>
<id>urn:sha1:c6a35733b74aeff612398f274ed19a74f81d1f37</id>
<content type='text'>
The cold_init() functions of ACLINT drivers should skip the HART
if sbi_hartid_to_scratch() returns NULL because we might be dealing
with a HART that is disabled in the device tree.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Use scratch space to save per-HART MTIMER pointer</title>
<updated>2023-06-05T11:16:50Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-04-19T15:57:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=f0516beae068ffce0d5a79f09a96904a661a25ba'/>
<id>urn:sha1:f0516beae068ffce0d5a79f09a96904a661a25ba</id>
<content type='text'>
Instead of using a global array indexed by hartid, we should use
scratch space to save per-HART MTIMER pointer.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Use heap in ACLINT MTIMER driver</title>
<updated>2023-06-05T10:28:42Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2023-04-19T11:43:22Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=7e5636ac3788451991a65791c5adcc7798dcc22a'/>
<id>urn:sha1:7e5636ac3788451991a65791c5adcc7798dcc22a</id>
<content type='text'>
Let's use heap allocation in ACLINT MTIMER driver instead of using
a fixed size global array.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>lib: utils: Improve fdt_timer</title>
<updated>2023-05-26T07:17:22Z</updated>
<author>
<name>Xiang W</name>
<email>wxjstz@126.com</email>
</author>
<published>2023-05-22T05:18:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=122f2260b350e94e4e79439ea289f08a329eb14a'/>
<id>urn:sha1:122f2260b350e94e4e79439ea289f08a329eb14a</id>
<content type='text'>
Remove dummy driver. Optimize fdt_timer_cold_init to exit the
loop early.

Signed-off-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
</feed>
