opensbi.git/lib/utils, branch release-1.8.x

lib: utils/serial: Support multiple UART8250 devices

2025-12-21T15:32:44Z

Previously we assume only 1 UART8250 instance can be used. Now we support multiple instances by introducing counterpart functions to putc/getc/init which take an extra *dev parameter, and name them as uart8250_device_xyz() The original functions without the *dev parameter will operate on the default instance exactly the same as before, so no changes on the caller is required. Note: uart8250_device_init only does device initialization without the console registration logic. Signed-off-by: Bo Gan Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251218104243.562667-7-ganboing@gmail.com Signed-off-by: Anup Patel

lib: utils: Use SBI_DOMAIN_MMIO to check MMIO device permissions

2025-12-08T11:17:55Z

Drivers or platforms may create memory regions with the MMIO flag set that contain S-mode-accessible MMIO devices. This is strictly correct and should be allowed, along with the existing default case of S-mode-accessible MMIO devices appearing in non-MMIO memory regions. When passed SBI_DOMAIN_MMIO, sbi_domain_check_addr() will perform the correct set of permission checks. Signed-off-by: Samuel Holland Reviewed-by: Yu-Chien Peter Lin Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251121193808.1528050-3-samuel.holland@sifive.com Signed-off-by: Anup Patel

lib: utils/cache: Add SiFive Extensible Cache (EC) driver

2025-12-08T04:31:20Z

Add support for SiFive Extensible Cache (EC) controller with multi-slice architecture. The driver implements cache maintenance operations through MMIO register interface. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Samuel Holland Signed-off-by: Samuel Holland Co-developed-by: Yong-Xuan Wang Signed-off-by: Yong-Xuan Wang Signed-off-by: Nick Hu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-3-8423a721924c@sifive.com Signed-off-by: Anup Patel

lib: utils/cache: Add SiFive PL2 controller

2025-12-08T04:31:05Z

SiFive Private L2(PL2) cache is a private cache owned by each hart. Add this driver to support private cache flush operations via the MMIO registers. Co-developed-by: Eric Lin Signed-off-by: Eric Lin Co-developed-by: Zong Li Signed-off-by: Zong Li Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Samuel Holland Signed-off-by: Samuel Holland Signed-off-by: Nick Hu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-2-8423a721924c@sifive.com Signed-off-by: Anup Patel

lib: utils/cache: Handle last-level cache correctly in fdt_cache_add()

2025-12-08T04:21:53Z

The fdt_cache_add() helper attempts to retrieve the next-level cache and returns SBI_ENOENT when there is none. Since this condition only indicates that the current cache is the last-level cache, the helper should not treat it as an error. Signed-off-by: Nick Hu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-1-8423a721924c@sifive.com Signed-off-by: Anup Patel

lib: utils/irqchip: plic: context_id is signed

2025-11-10T08:14:17Z

Array context_id in struct plic_data has elements of type s16. A negative valid indicates an invalid entry. Copying the array element to a u32 scalar hides the sign. Use s16 as target type when copying an array element to a scalar. Addresses-Coverity-ID: 1667176 Unsigned compared against 0 Addresses-Coverity-ID: 1667178 Logically dead code Addresses-Coverity-ID: 1667179 Unsigned compared against 0 Addresses-Coverity-ID: 1667182 Logically dead code Signed-off-by: Heinrich Schuchardt Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251105110121.47130-1-heinrich.schuchardt@canonical.com Signed-off-by: Anup Patel

lib: utils/serial: typo Recieve

2025-11-10T08:13:27Z

%s/Recieve/Receive/ Signed-off-by: Heinrich Schuchardt Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251105011648.9413-1-heinrich.schuchardt@canonical.com Signed-off-by: Anup Patel

lib: utils/timer: mtimer: add MIPS P8700 compatible

2025-11-10T08:11:53Z

The MTIMER of the MIPS P8700 is compliant with the ACLINT specification, so add a compatible string for it. Signed-off-by: Benoît Monin Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251107-p8700-aclint-v3-2-93eabb17d54e@bootlin.com Signed-off-by: Anup Patel

lib: utils/timer: mtimer: Select the reference mtimer from a DT property

2025-11-10T08:11:53Z

The current selection of the reference MTIMER may fail in some setup. In a multi-cluster configuration, there is one MTIMER per cluster, each associated with the HARTS of the cluster. So we do not have a MTIMER with no associated HARTs to use as our reference. To be able to select a reference MTIMER in that case, look up an optional device tree property named "riscv,reference-mtimer" that indicate which MTIMER is the reference. Signed-off-by: Benoît Monin Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251107-p8700-aclint-v3-1-93eabb17d54e@bootlin.com Signed-off-by: Anup Patel

lib: utils/ipi: mswi: add MIPS P8700 compatible

2025-11-05T16:07:37Z

The MSWI present in the MIPS P8700 is compliant with the ACLINT specification, so add a dedicated compatible string for it. Signed-off-by: Benoît Monin Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20251027-p8700-aclint-v2-1-f10cbfb66e92@bootlin.com Signed-off-by: Anup Patel