opensbi.git/lib/utils, branch v1.1

lib: utils/timer: Remove Allwinner D1 CLINT compatibles

2022-06-22T05:25:37Z

The allwinner,sun20i-d1-clint compatible string is not documented in any official binding, so it should not be used by drivers. The MSWI in the D1 CLINT is compatible with the ACLINT specification, so it can take advantage of generic driver support. However, that is only possible if the MSWI and MTIMER are split into separate DT nodes. This means the final binding for this device is likely to be incompatible with what is implemented here. Remove this compatible string from the driver to prevent it from appearing in a stable version and causing future issues. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel

lib: irqchip/plic: fix typo in plic_warm_irqchip_init

2022-06-22T05:25:27Z

The second invocation of plic_context_init() incorrectly calls the function with m_cntx_id instead of s_cntx_id. This breaks systems which only have 1 external interrupt per hart. Fixes: 8c362e7 ("lib: irqchip/plic: Factor out a context init function") Signed-off-by: Jan Remes Reviewed-by: Anup Patel Reviewed-by: Samuel Holland

lib: utils/timer: Add a separate compatible for the D1 CLINT

2022-06-21T03:50:59Z

The CLINT in the Allwinner D1 SoC apparently does not support 64-bit MMIO access. A property was added to support this quirk (and that property was copied to the ACLINT MTIMER code). However, since this difference in behavior makes the D1 CLINT incompatible with the SiFive CLINT's programming interface, a better solution is to use a separate compatible string. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel

lib: utils: Remove CSRs that set/clear an IMSIC interrupt file bits

2022-06-21T03:14:45Z

Based on architecture review committee feedback, the [m|s|vs]seteienum, [m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are removed in the latest AIA draft v0.3.0 specification. (Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31) These CSRs were mostly for software convenience and software can always use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt file bits. We update the IMSIC programming as-per above to match the latest AIA draft specification. Signed-off-by: Anup Patel Reviewed-by: Atish Patra

lib: utils/irqchip: Add wrapper for T-HEAD PLIC delegation

2022-06-13T06:24:06Z

The delegation bit is lost along with the rest of the PLIC state when the CPU power domain in the Allwinner D1 is powered down, so the PLIC needs to be re-delegated to S-mode during the hart resume path. Reviewed-by: Anup Patel Signed-off-by: Samuel Holland

lib: utils/irqchip: Add FDT wrappers for PLIC save/restore functions

2022-06-13T06:24:06Z

These functions save/restore the state of the PLIC associated with the current hart. The context save/restore functions only manipulate a single context, since most likely the M-mode context is unused and does not need to be saved. Signed-off-by: Samuel Holland Reviewed-by: Anup Patel

lib: irqchip/plic: Add priority save/restore helpers

2022-06-13T06:24:06Z

These can be used by platform code to save the PLIC priority state, if it would otherwise be lost during non-retentive suspend. The platform is responsible for allocating all necessary storage. As a space optimization, store the saved priority values as 8-bit integers, since that is large enough to hold any priority value on the relevant platforms. Reviewed-by: Anup Patel Signed-off-by: Samuel Holland

lib: irqchip/plic: Add context save/restore helpers

2022-06-13T06:24:06Z

These can be used by platform code to save the PLIC context state, if it would otherwise be lost during non-retentive suspend. The platform is responsible for allocating all necessary storage. Reviewed-by: Anup Patel Signed-off-by: Samuel Holland

lib: irqchip/plic: Factor out a context init function

2022-06-13T06:24:06Z

This simplifies both the callers and the callees by removing duplicated code and consolidating the error handling. It also fixes two bugs in the process: 1) ie_words was one too large when plic->num_src was a multiple of 32. 2) plic_set_ie takes a 32-bit mask, not a Boolean value, so the FPGA platforms previously only enabled one out of every 32 interrupts. Reviewed-by: Anup Patel Signed-off-by: Samuel Holland

lib: irqchip/plic: Constify plic_data pointers

2022-06-13T06:24:06Z

None of the functions modify the passed-in plic_data, so mark it const. Reviewed-by: Anup Patel Signed-off-by: Samuel Holland