opensbi.git/lib/utils, branch v1.2

lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible

2022-12-17T05:31:06Z

As we already added the quirk for lacking mtime register to MTIMER driver, add T-Head C9xx CLINT compatible to it and wire the quirk. Signed-off-by: Icenowy Zheng Reviewed-by: Anup Patel

lib: utils/timer: mtimer: add a quirk for lacking mtime register

2022-12-17T05:31:03Z

T-Head developers surely have a different understanding of time CSR and CLINT's mtime register with SiFive ones, that they did not implement the mtime register at all -- as shown in openC906 source code, their time CSR value is just exposed at the top of their processor IP block and expects an external continous counter, which makes it not overrideable, and thus mtime register is not implemented, even not for reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS extended CSR, these systems still rely on the mtimecmp registers to generate timer interrupts. This makes it necessary to implement T-Head C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing reading mtime register and falls back to default code that reads time CSR. Add a quirk into MTIMER driver, which represents a mtime register is lacking and time CSR value should be used instead. Signed-off-by: Icenowy Zheng Reviewed-by: Anup Patel

lib: utils/ipi: mswi: add T-Head C9xx CLINT compatible

2022-12-17T05:31:00Z

Althoug the MTIMER part of a C9xx CLINT differs from a SiFive one, the MSWI part is compliant. Add T-Head C9xx CLINT compatible string to fdt_ipi_mswi code, sharing the same codepath with SiFive CLINT. Signed-off-by: Icenowy Zheng Reviewed-by: Anup Patel

lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers

2022-12-17T03:33:30Z

Currently the context save/restore helpers writes/reads the provided array using an index whose maximum value is determined by PLIC, which potentially may disagree with the caller to these helpers. Add a parameter to ask the caller to provide the size limit of the array to ensure no out-of-bound access happens. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

lib: utils/irqchip: plic: Fix the off-by-one error in context save/restore helpers

2022-12-17T03:32:40Z

plic->num_src holds the number of interrupt sources without interrupt source 0 but the interrupt enable register includes a bit for the interrupt source 0 in the first word. Fixes: 415ecf28f7ad ("lib: irqchip/plic: Add context save/restore helpers") Signed-off-by: Bin Meng Reviewed-by: Anup Patel Reviewed-by: Samuel Holland

lib: utils/irqchip: plic: Fix the off-by-one error in plic_context_init()

2022-12-17T03:30:35Z

The number of interrupt enable register in words was once correct, but was wrongly changed to have an off-by-one error since commit 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function"). Fixes: 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function") Signed-off-by: Bin Meng Reviewed-by: Anup Patel Reviewed-by: Samuel Holland

lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers

2022-12-17T03:30:29Z

Currently the priority save/restore helpers writes/reads the provided array using an index whose maximum value is determined by PLIC, which potentially may disagree with the caller to these helpers. Add a parameter to ask the caller to provide the size limit of the array to ensure no out-of-bound access happens. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

lib: utils/irqchip: plic: Fix the off-by-one error in priority save/restore helpers

2022-12-17T03:12:21Z

Interrupt source 0 is reserved. Hence the irq should start from 1. Fixes: 2b79b694a805 ("lib: irqchip/plic: Add priority save/restore helpers") Signed-off-by: Bin Meng Reviewed-by: Anup Patel

lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100

2022-12-12T13:20:46Z

Add compatible string for Andestech NCEPLIC100 found on Renesas RZ/Five SoC which is equipped with AX45MP AndesCore. While at it drop the comma after the sentinel as it does not make sense to have a comma after a sentinel, as any new elements must be added before the sentinel. dts example (Single-core AX45MP): soc: soc { .... plic: interrupt-controller@12c00000 { compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; #interrupt-cells = <2>; #address-cells = <0>; riscv,ndev = <511>; interrupt-controller; reg = <0x0 0x12c00000 0 0x400000>; clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; power-domains = <&cpg>; resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; }; .... }; Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel Reviewed-by: Bin Meng

lib: utils: serial: Add FDT driver for Renesas SCIF

2022-12-12T13:20:35Z

Add FDT driver for Renesas SCIF. dts example: soc: soc { .... scif0: serial@1004b800 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004b800 0 0x400>; interrupts = <412 IRQ_TYPE_LEVEL_HIGH>, <414 IRQ_TYPE_LEVEL_HIGH>, <415 IRQ_TYPE_LEVEL_HIGH>, <413 IRQ_TYPE_LEVEL_HIGH>, <416 IRQ_TYPE_LEVEL_HIGH>, <416 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; clock-names = "fck"; power-domains = <&cpg>; resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; status = "disabled"; }; .... }; Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel