opensbi.git/lib/utils, branch v1.4

lib: utils/timer: mtimer: only use regname for aclint

2023-12-27T06:27:33Z

The parser will fail if the timer is clint timer and has regname property. As the regname is only meaningful for aclint, it is more robust to only check regname for aclint timer. Fixes: 6112d58 ("lib: utils/fdt: Allow to use reg-names when parsing ACLINT") Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel

lib: utils/irqchip: Add shared MMIO region for PLIC in root domain

2023-12-19T10:26:37Z

On platforms with Smepmp, the MMIO regions accessed by M-mode need to be explicitly marked with M-mode only read/write or shared (both (M-mode and S-mode) read/write permission. If the above is not done then runtime PLIC access from M-mode on platforms with Smepmp will result in access fault when further results in CPU hotplug not working. Signed-off-by: Anup Patel

lib: sbi: Using one array to define the name of extensions

2023-12-19T08:44:22Z

Define an array sbi_hart_ext to map extension ID and name , and use it for ISA parsing and printing out the supported extensions. Signed-off-by: Yong-Xuan Wang Reviewed-by: Anup Patel

lib: utils/fdt: Allow to use reg-names when parsing ACLINT

2023-12-11T05:05:32Z

Currently, the fdt_parse_aclint_node() follows a fixed order to parse ACLINT timer. This may cause the undesirable result when the ACLINT device does not support mtime without adding an empty entry for it in the DT. To be robust, make fdt_parse_aclint_node() support "reg-names" property, so it can parse the DT in an order independent way. For compatibility, fdt_parse_aclint_node() only use "reg-names" when parsing ACLINT timer, and will fallback to the old way if "reg-names" property is not found. Link: https://lore.kernel.org/all/20231114-skedaddle-precinct-66c8897227bb@squawk/ Signed-off-by: Inochi Amaoto Reviewed-by: Anup patel

lib: utils: fdt_pmu: Do not iterate over the fdt_pmu_evt_select table

2023-12-06T12:47:08Z

The valid entry count is tracking by hw_event_count so there is no need to check the whole table. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Atish Patra Reviewed-by: Anup Patel

lib: utils: fdt_pmu: Make the fdt_pmu_evt_select table global variable

2023-12-06T12:45:41Z

To allow platform override pmu_init() filling the translation table fdt_pmu_evt_select[] when PMU node doesn't provide such information, we need to share the table and its entry counter with other .c file. We also define the structures of PMU property in fdt_helper.h, so we can initialize the mappings in arrays. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Atish Patra Reviewed-by: Anup Patel

lib: utils: fdt_fixup: Allow preserving PMU properties

2023-12-06T12:29:44Z

Add a Kconfig option to control PMU fixup, so the next stage software can dump the PMU node including event mapping information for debugging purposes. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Atish Patra Reviewed-by: Anup Patel

sbi: sbi_pmu: Improve sbi_pmu_init() error handling

2023-12-06T11:54:38Z

This patch makes the following changes: - As sbi_platform_pmu_init() returns a negative error code on failure, let sbi_pmu_init() print out the error code with sbi_dprintf(). - In order to distinguish the SBI_EFAIL error returned by sbi_pmu_add_*_counter_map(), return SBI_ENOENT to indicate that fdt_pmu_setup() failed to locate "riscv,pmu" node, and generic_pmu_init() ignores such case. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel Reviewed-by: Lad Prabhakar Reviewed-by: Atish Patra

lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme

2023-12-06T11:53:27Z

The old scheme doesn't allow sending hart0 self-IPI as the corresponding bit on pending register is hardwired to 0, this could lead to unhandle IPIs on SMP systems, esp. on single-core. Furthermore, the limitation of old scheme is 8-core, instead of reserving source hart information, we assign bit (x + 1) as the enable and pending bit of hartx, this also expands the bootable hart number. The following diagram shows the enable bits of the new scheme on 32-core Andes platform. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> To send IPI to hart0, for example, another hart (including hart0 itself) will set bit 1 of first word on the pending register. We also fix indentation in andes_plicsw.h along with this patch. Fixes: ce7c490719ed ("lib: utils/ipi: Add Andes fdt ipi driver support") Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin Reviewed-by: Randolph Reported-by: Lad Prabhakar Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005665.html Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar Reviewed-by: Anup Patel

lib: sbi: Allow relaxed MMIO writes in device ipi_clear() callback

2023-11-26T13:15:08Z

Currently, there are no barriers before or after the ipi_clear() device callback which forces ipi_clear() device callback to always use non-relaxed MMIO writes. Instead of above, we use wmb() in after the ipi_clear() device callback which pairs with the wmb() done before the ipi_send() device callback. This also allows device ipi_clear() callback to use relaxed MMIO writes. Signed-off-by: Anup Patel Reported-by: Bo Gan