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<title>opensbi.git/lib/utils, branch v1.9</title>
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<id>http://cgit.235523.xyz/opensbi.git/atom/lib/utils?h=v1.9</id>
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<updated>2026-06-15T04:40:25Z</updated>
<entry>
<title>lib: utils/reset: Add litex SoC reset driver</title>
<updated>2026-06-15T04:40:25Z</updated>
<author>
<name>Inochi Amaoto</name>
<email>inochiama@gmail.com</email>
</author>
<published>2026-05-29T08:52:32Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=dec9141a77058dc941f2d0f07107f7306a995c35'/>
<id>urn:sha1:dec9141a77058dc941f2d0f07107f7306a995c35</id>
<content type='text'>
Litex SoC controller supports reboot function by toggling the first
bit of the ctrl register. Add a reset driver so other software can
use it.

Signed-off-by: Inochi Amaoto &lt;inochiama@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260529085234.1682842-1-inochiama@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: generic: Optimize extensions_init() to parse ISA extensions once</title>
<updated>2026-06-12T10:38:29Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-05-21T08:26:25Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=ecc92e87a990e3f45081fbf2c84ad342d9226aaa'/>
<id>urn:sha1:ecc92e87a990e3f45081fbf2c84ad342d9226aaa</id>
<content type='text'>
Instead of parsing ISA extensions separately for each hart in the
generic_extensions_init() function, it is better to parse ISA extensions
for all available harts in the cold boot path. Also, this allows us
to remove fdt_isa_bitmap from scratch space and directly initialize
"extensions" in struct sbi_hart_features for each hart.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260521082625.1520870-3-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_irqchip: Allow irqchip drivers advertise capabilities</title>
<updated>2026-06-10T12:43:10Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-06-08T12:52:53Z</published>
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<id>urn:sha1:8570b938444d92d4557df7e03bd9cb83fdd4c2b1</id>
<content type='text'>
Extend struct sbi_irqchip_device to allow irqchip drivers advertise
interrupt controller capabilities (such as wired interrupt, MSIs, etc).
This further allows other parts of OpenSBI to lookup irqchip devices
based on capabilities.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260608125257.3220114-2-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/reset: Remove unused match data</title>
<updated>2026-05-22T05:01:41Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2026-05-13T22:44:12Z</published>
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<id>urn:sha1:547a5bbda7c3ec0096a6c87809851f8c2df047d1</id>
<content type='text'>
Some drivers inherited FDT match data from the GPIO/syscon reset
drivers, but do not use it for anything. Remove it to avoid confusion.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260513224414.1078791-1-samuel.holland@sifive.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils: fdt_domain: add root-regions-inheritance policy</title>
<updated>2026-05-18T12:50:50Z</updated>
<author>
<name>Yu-Chien Peter Lin</name>
<email>peter.lin@sifive.com</email>
</author>
<published>2026-05-16T07:29:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=f36acaeb80a490339923a5ec01ac3707741f6b90'/>
<id>urn:sha1:f36acaeb80a490339923a5ec01ac3707741f6b90</id>
<content type='text'>
Introduce root-regions-inheritance DT property to control
copying of root domain memregions. Support 'all' and 'm-only'
modes, always inheriting firmware and M-only regions; behavior
matches m-only policy when property is absent.

Signed-off-by: Yu-Chien Peter Lin &lt;peter.lin@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260516072906.1427203-1-peter.lin@sifive.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_irqchip: Allow marking hardware interrupts as reserved</title>
<updated>2026-05-12T04:25:58Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-04-23T05:23:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=d861447b0b0297db5fbe28878f8568a93fcfa965'/>
<id>urn:sha1:d861447b0b0297db5fbe28878f8568a93fcfa965</id>
<content type='text'>
Some of the hardware interrupts may be special so allow irqchip
drivers to make these hardware interrupts as reserved. Introduce
sbi_irqchip_register_reserved() for this purpose.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260423052339.356900-5-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_irqchip: Allow interrupt client to specify line sensing</title>
<updated>2026-05-12T04:25:58Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@oss.qualcomm.com</email>
</author>
<published>2026-04-23T05:23:36Z</published>
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<id>urn:sha1:adb4caf765cc977c8de6534d0bf77df9dd243e41</id>
<content type='text'>
The interrupt client should be allowed to specify the line sensing
type of the hwirqs for which it is registering handler. To support
this, add hwirq_flags parameter to hwirq_setup() callback provided
by the irqchip driver.

Signed-off-by: Anup Patel &lt;anup.patel@oss.qualcomm.com&gt;
Link: https://lore.kernel.org/r/20260423052339.356900-4-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/reset: add SpacemiT P1 PMIC support</title>
<updated>2026-05-11T13:51:31Z</updated>
<author>
<name>Aurelien Jarno</name>
<email>aurelien@aurel32.net</email>
</author>
<published>2026-04-19T14:49:20Z</published>
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<id>urn:sha1:d9637d00bf47a3cc17306fc62e71652c8a83c289</id>
<content type='text'>
The SpacemiT P1 is a PMIC commonly found with SpacemiT CPU like K1. Add
a reset driver for it.

Signed-off-by: Aurelien Jarno &lt;aurelien@aurel32.net&gt;
Tested-by: Anand Moon &lt;linux.amoon@gmail.com&gt;
Link: https://lore.kernel.org/r/20260419150857.2705843-3-aurelien@aurel32.net
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/i2c: add minimal SpacemiT I2C driver</title>
<updated>2026-05-11T13:51:31Z</updated>
<author>
<name>Aurelien Jarno</name>
<email>aurelien@aurel32.net</email>
</author>
<published>2026-04-19T14:49:19Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=b10e18ec854a80e938a1fc8cf23beb8f8577cbaf'/>
<id>urn:sha1:b10e18ec854a80e938a1fc8cf23beb8f8577cbaf</id>
<content type='text'>
Add a simple SpacemiT I2C driver for basic byte transfers over the I2C
bus, prioritizing simplicity over performance. The driver operates in
PIO mode and does not use interrupts, FIFO, or DMA.

The controller is reset at the start of each transaction to ensure a
known initial state, regardless of prior configuration by the kernel.
This also avoids the need for additional error recovery code.

This will be used for communication with onboard PMIC to reset and
power-off the board.

Signed-off-by: Aurelien Jarno &lt;aurelien@aurel32.net&gt;
Tested-by: Anand Moon &lt;linux.amoon@gmail.com&gt;
Link: https://lore.kernel.org/r/20260419150857.2705843-2-aurelien@aurel32.net
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/regmap: Fix reg_stride calculation in syscon regmap</title>
<updated>2026-05-11T06:19:59Z</updated>
<author>
<name>David E. Garcia Porras</name>
<email>david.garcia@aheadcomputing.com</email>
</author>
<published>2026-04-03T20:29:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=8536a351fd3af50e5eba571e562a33247b99870d'/>
<id>urn:sha1:8536a351fd3af50e5eba571e562a33247b99870d</id>
<content type='text'>
The reg_stride field represents the address stride in bytes between
consecutive registers. The Linux kernel regmap framework validates
register accesses using IS_ALIGNED(reg, map-&gt;reg_stride) as an address
alignment check (drivers/base/regmap/regmap.c). The Linux kernel syscon
driver (drivers/mfd/syscon.c) sets reg_stride directly to reg_io_width:

  syscon_config.reg_stride = reg_io_width;

The current OpenSBI code incorrectly multiplies reg_io_width by 8,
converting a byte value to bits. Fix this by using reg_io_width directly
as the stride value, consistent with the Linux kernel.

Fixes: f21d8f7d5911 ("lib: utils/regmap: Add simple FDT based syscon regmap driver")
Signed-off-by: David E. Garcia Porras &lt;david.garcia@aheadcomputing.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20260403202903.3407945-1-david.garcia@aheadcomputing.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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