opensbi.git/lib, branch master

lib: utils/mpxy: bind channel access to owning domain

2026-07-22T08:28:30Z

The MPXY framework currently stores registered channels in a global list and exposes them to all callers. However, the intended model is that each channel is assigned to a single supervisor domain at boot and remains owned by that domain for its lifetime. Introduce fixed owner-domain tracking in struct sbi_mpxy_channel and make channel lookup and enumeration domain-aware. A channel is now visible only when accessed from its owning domain. Also require the owner to be set before channel registration. This allows MPXY to support systems where the same hart may be reused by multiple domains while keeping channel ownership and visibility fixed to the domain that owns the service. Signed-off-by: Oza Pawandeep Reviewed-by: Rahul Pathak Link: https://lore.kernel.org/r/20260721215758.695736-1-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_irqchip: fix MSI EIID gap and tail allocation logic in register_msi

2026-07-22T07:50:22Z

Fix sbi_irqchip_register_msi() that prevented contiguous EIID allocation: - Gap check condition was inverted: the original `h->first_hwirq - hwirq < num_hwirq` incorrectly set `found = true` when the gap was too small to fit num_hwirq entries. Correct to `>= num_hwirq` so allocation only proceeds when sufficient space exists between registered handlers. - Tail-space check `!found && !hwirq` never triggered after iteration Replace with `(chip->num_hwirq - hwirq) >= num_hwirq` to correctly allocate if handler list is empty. Fixes: 79e63bc8348d ("irqchip: add sbi_irqchip_register_msi support") Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-7-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/imsic: track IRQ enable state and restore EIE on warm init

2026-07-22T07:50:20Z

Add an irq_state field to struct sbi_irqchip_hwirq_data with a single IRQ_ENABLED flag (bit 0) to track whether a hardware interrupt has been enabled via the irqchip framework. Set IRQ_ENABLED in sbi_irqchip_unmask_hwirq() when the unmask callback is invoked. Add sbi_irqchip_get_irq_state() as a private inline accessor and expose sbi_irqchip_is_irq_enabled() as a public API for drivers to query the enabled state of a hardware interrupt by chip pointer and hwirq number. Refactor imsic_local_eix_update() to operate on a single interrupt ID instead of a base+count range, simplifying the CSR bit manipulation to a direct BIT(id) write without the inner loop. Update all call sites accordingly. Use sbi_irqchip_is_irq_enabled() in imsic_warm_irqchip_init() to restore per-EIID EIE CSR state on warm boot and HSM resume based on the saved irq_state, replacing the previous blanket disable of all interrupts. This ensures that EIIDs enabled during hotplug/warminit cycle are correctly re-enabled on the resuming hart without requiring software to re-register or re-unmask each interrupt. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-6-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/imsic:migrate to irqchip framework

2026-07-22T07:50:14Z

Rewrite imsic_process_hwirqs() to use container_of() for instance lookup, validate ownership via imsic_current_hart_owner(), mask IMSIC_TOPEI_ID_MASK on the raw CSR value, and dispatch non-IPI EIIDs through sbi_irqchip_process_hwirq() instead of an open-coded switch. Rewrite imsic_warm_irqchip_init() to resolve the imsic_data instance via container_of() from the sbi_irqchip_device pointer, and skip initialization silently for harts not owned by this instance. Extend the sbi_irqchip callback set: - hwirq_setup: registers sbi_irqchip_raw_handler_default for the EIID - hwirq_cleanup: clears EIE and EIP bits for the EIID on the owner hart - hwirq_eoi: no-op as claim/ack is already performed by CSR_MTOPEI read in imsic_process_hwirqs() - hwirq_set_affinity: reprograms the upstream MSI source via imsic_program_msi() to retarget the interrupt to the new hart - hwirq_mask: clears the EIE bit for the EIID on the owner hart - hwirq_unmask: sets the EIE bit for the EIID on the owner hart, skipping IPI (EIID 1) and non-owner harts Add imsic_compose_msi_msg() to compute the MMIO target address for a given hart and EIID by walking the imsic_regs array and applying file and guest index offsets. Add imsic_program_msi() that composes an MSI message and delivers it to the upstream interrupt source via sbi_irqchip_write_msi(), enabling APLIC TARGET register programming from the IMSIC driver. Migrate imsic_cold_irqchip_init() to the instance-based model: preserve any pre-configured target_harts mask set by platform or FDT code before applying the imsic_device template, falling back to sbi_hartmask_set_all() only when no mask was provided. Register the irqchip and reserved EIIDs on the embedded irqchip rather than the global singleton. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-5-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/imsic: embed sbi_irqchip_device in imsic data

2026-07-22T07:38:15Z

Embed sbi_irqchip_device in struct imsic_data to enable instance-based irqchip registration, replacing the previous global imsic_device singleton. Include sbi_irqchip.h from imsic.h to make the embedded struct visible to consumers. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-4-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/aplic: add MSI mode support with IMSIC parent linking

2026-07-22T07:38:13Z

Add parent_unique_id fields to struct aplic_data for IMSIC parent linking in MSI mode. Store parent IMSIC unique_id during FDT parsing of the APLIC node. Add aplic_is_msi_mode() complementing aplic_is_direct_mode() to consolidate delivery mode detection. Add APLIC_TARGET_EIID() macro for packing the EIID field into the TARGET register. Add parent_unique_id and parent_irq_map fields to struct aplic_data. parent_unique_id identifies the upstream IMSIC irqchip device resolved via sbi_irqchip_find_device() during hwirq_setup. parent_irq_map is a per-source array allocated at cold init time to track the EIID assigned by the IMSIC for each APLIC source. Restore aplic_writel_msicfg() and re-introduce MSI address register programming in aplic_init(), gated on aplic_is_msi_mode(). Set the DOMAINCFG_DM bit to switch the hardware to MSI delivery mode when no IDC structures are present. Add aplic_program_msi_target() to pack hart_index, guest_index, and EIID into the APLIC_TARGET register. Add aplic_write_msi() as the sbi_irqchip write_msi callback that extracts EIID and hart_index from the MSI message and calls aplic_program_msi_target(). Add aplic_msi_callback() as the MSI receive callback that dispatches to sbi_irqchip_process_hwirq() on the APLIC chip. Extend aplic_hwirq_setup() with an MSI path that resolves the parent IMSIC chip by parent_unique_id, registers an MSI route via sbi_irqchip_register_msi(), and stores the allocated EIID in parent_irq_map for the source being configured. Extend aplic_hwirq_set_affinity() with an MSI path that delegates affinity reprogramming to the parent IMSIC chip via sbi_irqchip_set_affinity() using the stored parent_irq_map entry. Guard warm_init, process_hwirqs, and hwirq_eoi with early returns in MSI mode as interrupt delivery and acknowledgement are handled by the IMSIC in that configuration. Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-3-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: utils/irqchip/aplic: implement direct mode irqchip callbacks

2026-07-22T07:37:40Z

Add inline register accessors (aplic_sourcecfg_write/read, aplic_target_write, aplic_irq_setie/clrie/clrip, aplic_idc_base/ read/write) to consolidate all MMIO access behind typed helpers and eliminate open-coded address arithmetic throughout the driver. Add field-packing macros APLIC_TARGET_HART_IDX, APLIC_TARGET_IPRIO, and APLIC_TARGET_GUEST_IDX for constructing APLIC_TARGET register values. Add aplic_is_direct_mode() mode helper, aplic_hwirq_flags_to_sourcecfg() to map generic hwirq flags to APLIC source modes, aplic_hwirq_is_delegated() to detect S-mode delegated sources, aplic_find_idc_index() to map a hart index to its IDC slot, and aplic_first_target_hart() to select the first available IDC hart for initial interrupt targeting. Implement the full sbi_irqchip callback set for direct (IDC) mode: - warm_init: enables IDC interrupt delivery and threshold per hart - process_hwirqs: reads TOPI and dispatches via sbi_irqchip_process_hwirq, skipping delegated sources - hwirq_setup: programs sourcecfg from hwirq_flags and sets the TARGET register to the first available IDC hart - hwirq_cleanup: clears IE, IP, sourcecfg, and TARGET on teardown - hwirq_eoi: reads CLAIMI to acknowledge the interrupt on the IDC - hwirq_set_affinity: reprograms TARGET to the specified hart index - hwirq_mask/unmask: clears/sets IE via CLRIENUM/SETIENUM Register the irqchip device and populate target_harts from idc_map only when targets_mmode is set in aplic_cold_irqchip_init(). Co-developed-by: Raymond Mao Signed-off-by Raymond Mao Signed-off-by: Oza Pawandeep Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260721214833.687361-2-pawandeep.oza@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi: Move trap delegation setup to sbi_trap.c

2026-07-21T06:20:46Z

Currently, the trap delegation setup is part of sbi_hart.c and called via sbi_hart_init() whereas the per-hart trap (aka exception and interrupt) handling is part of sbi_trap.c. Move trap delegation init to sbi_trap.c and call it via new sbi_trap_init() from both cold boot and warm boot path. This way trap delegation setup is in same place as trap handling. Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20260613132129.2135128-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel

lib: sbi_ipi: Validate hartids against domain, not HSM state

2026-07-21T05:58:59Z

Commit 37eaca4ab33d ("lib: sbi_ipi: Return error for invalid hartids") added a weight check against the HSM-interruptible mask, which excludes harts in STOPPED state. This causes sbi_ipi_send_many() to return SBI_EINVAL when the kernel sends a remote fence (e.g. TLB shootdown) whose hmask includes a hart that was stopped by CPU hotplug: __sbi_rfence_v02_call: hbase = [0] hmask = [0x3] failed (error [-22]) Validate requested hartids against the domain's assigned hartmask instead. This still rejects truly invalid or cross-domain hartids, but allows HSM-STOPPED harts to be silently skipped — which is safe because a stopped hart will do a full local TLB flush on its next HSM start before re-entering S-mode. Fixes: 37eaca4ab33d ("lib: sbi_ipi: Return error for invalid hartids") Signed-off-by: Chen Pei Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260612115208.118132-1-cp0613@linux.alibaba.com Signed-off-by: Anup Patel

lib: sbi_irqchip: fix device lookup by caps when first is NULL

2026-07-16T05:57:57Z

When called with first == NULL, sbi_irqchip_find_device_by_caps() should scan the device list from the start. Instead it always returns NULL: "found" starts false and only flips true when an entry equals "first", but no entry ever equals NULL, so every entry hits "else continue" and nothing is checked. This breaks MSI detection in sbi_mpxy, which calls it with first == NULL: ms->msi_avail = !!sbi_irqchip_find_device_by_caps(SBI_IRQCHIP_CAPS_MSI, NULL); msi_avail is therefore always false, so mpxy_write_std_attr() silently drops the MSI attributes (MSI_ADDR_LO/HI, MSI_DATA, MSI_CONTROL) while still returning success, and MSI-based MPXY notifications are never delivered. Initialize "found" from "first" so a NULL "first" scans from the beginning, and always continue in the pre-match branch so a non-NULL "first" resumes after the given device. Fixes: 8570b938444d ("lib: sbi_irqchip: Allow irqchip drivers advertise capabilities") Signed-off-by: David E. Garcia Porras Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260701181334.969877-1-david.garcia@aheadcomputing.com Signed-off-by: Anup Patel