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<title>opensbi.git/lib, branch v0.8</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2020-06-20T05:06:13Z</updated>
<entry>
<title>lib: Don't return any invalid error from SBI ecall</title>
<updated>2020-06-20T05:06:13Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-06-10T13:09:53Z</published>
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<id>urn:sha1:2314101989684585f942b50a827aac4886825ba1</id>
<content type='text'>
We should only return valid error codes from SBI ecalls as
defined by the RISC-V SBI spec.

To achieve this:
1. We use SBI_Exxxx defines for OpenSBI internal errors with
   error values starting from -1000
2. We use SBI_ERR_xxxx defines for errors defined by SBI spec
3. We map some of the SBI_Exxxx defines to SBI_ERR_xxxx defines
   which are semantically same
4. We throw a error print and force return error code to
   SBI_ERR_FAILED in sbi_ecall_handler() if we see an invalid
   error code being returned to S-mode

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Fix 32/64 bits variable compatibility</title>
<updated>2020-06-20T03:17:11Z</updated>
<author>
<name>Liush</name>
<email>liush.damon@gmail.com</email>
</author>
<published>2020-06-19T03:55:19Z</published>
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<id>urn:sha1:9bd5f8f17d31f8989525643a04da87d090fe3033</id>
<content type='text'>
On RV64,"unsigned long" is 64bit and "unsigned int" is 32bit. So in
function "pmp_get" and "pmp_set", if "pmpcfg_shift &gt;= 32", "0xff &lt;&lt; pmpcfg_shift"
will go beyond "unsigned int" width. This patch tries to fix this issue.

In function 'pmp_get':
	cfgmask = (0xff &lt;&lt; pmpcfg_shift);
			--&gt;
	cfgmask = (0xffUL &lt;&lt; pmpcfg_shift);
In function 'pmp_set':
	cfgmask = ~(0xff &lt;&lt; pmpcfg_shift);
			--&gt;
	cfgmask = ~(0xffUL &lt;&lt; pmpcfg_shift);

Signed-off-by: Liush &lt;liush.damon@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>platform: Add support for Shakti C-class SoC from IIT-M</title>
<updated>2020-06-19T03:51:46Z</updated>
<author>
<name>Vijai Kumar K</name>
<email>vijai@behindbytes.com</email>
</author>
<published>2020-06-17T13:55:16Z</published>
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<id>urn:sha1:db56ef367cd6dc9dab94076f4c8a3fa9d91bd1f2</id>
<content type='text'>
C-Class is a member of the SHAKTI family of processors from Indian
Institute of Technology - Madras(IIT-M).
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.

https://gitlab.com/shaktiproject/cores/c-class/blob/master/README.md

We add OpenSBI support for Shakti C-class SoC.

Signed-off-by: Vijai Kumar K &lt;vijai@behindbytes.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: Fix the SBI_HART_HAS_MCOUNTEREN feature check</title>
<updated>2020-06-18T03:28:13Z</updated>
<author>
<name>Alistair Francis</name>
<email>alistair.francis@wdc.com</email>
</author>
<published>2020-06-17T00:07:33Z</published>
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<id>urn:sha1:637b348224d557cd27c187d4465a90852ddde8a9</id>
<content type='text'>
Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: Don't print delegation CSRs if there is no S-Mode</title>
<updated>2020-06-18T03:26:54Z</updated>
<author>
<name>Alistair Francis</name>
<email>alistair.francis@wdc.com</email>
</author>
<published>2020-06-17T00:06:15Z</published>
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<id>urn:sha1:d5725c24c6ea04368d90bc0f5af3ec20862b4a3b</id>
<content type='text'>
If the platform doesn't support S-Mode don't print the delegation
registers.

Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>platform/lib: Allow the OS to map the regions that are protected by PMP</title>
<updated>2020-06-15T03:55:44Z</updated>
<author>
<name>Alexandre Ghiti</name>
<email>alex@ghiti.fr</email>
</author>
<published>2020-06-13T06:59:13Z</published>
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<id>urn:sha1:6966ad0abe7077b1b5c9342f588621426d997c38</id>
<content type='text'>
This is achieved by removing the 'no-map' property from the
'reserved-memory' node when PMP is present, otherwise we keep it as it
offers a small protection if the OS does not map this region at all.
A new callback in platform_override is introduced and allows to fixup the
device-tree. It is used here to override this new default behaviour on
SiFive Fu540 platforms that has an erratum that prevents S-mode software
to access a PMP protected region using 1GB page table mapping.

If PMP is present, telling the OS not to map the reserved regions does not
add much protection since it only avoids access to regions that are already
protected by PMP. But by not allowing the OS to map those regions, it
creates holes in the OS system memory map and prevents the use of
hugepages which would generate, among other benefits, less TLB miss.

Signed-off-by: Alexandre Ghiti &lt;alex@ghiti.fr&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: Fix __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_vvma_asid_va()</title>
<updated>2020-06-15T03:54:27Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-06-06T12:03:48Z</published>
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<id>urn:sha1:e2c3f01af4329aa7e9009edee13b7cfdf379071f</id>
<content type='text'>
The arguments/parameters of __sbi_hfence_gvma_vmid_gpa() and
__sbi_hfence_vvma_asid_va() functions are swapped so we fix it.

Currently, we did not face any issues because QEMU does a full
TLB flush for all HFENCE instructions.

We also improve documentation of HFENCE.GVMA and HFENCE.VVMA
instruction encoding.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: Add RISC-V hypervisor v0.6.1 support</title>
<updated>2020-06-08T10:11:23Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-05-28T03:07:42Z</published>
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<id>urn:sha1:1b8c0128f1d79d69ea0a46b758fef4be8dc0a73e</id>
<content type='text'>
To support RISC-V hypervisor v0.6.1, we:
1. Don't need to explicitly forward WFI traps from VS/VU-mode
2. Have to delegate virtual instruction trap to HS-mode
3. Have to update trap redirection for changes in HSTATUS CSR

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/timer: Initialize all matching timer DT nodes</title>
<updated>2020-05-23T05:06:53Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-05-13T07:41:44Z</published>
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<id>urn:sha1:a63f05f3dea6fde8b5d545c2c6a5762faa56539a</id>
<content type='text'>
We can have multiple matching DT nodes of the same FDT timer driver
so in this case we should call cold_init() for all matching DT nodes
instead of just first matching DT node.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/ipi: Initialize all matching ipi DT nodes</title>
<updated>2020-05-23T05:06:49Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2020-05-13T07:44:33Z</published>
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<id>urn:sha1:6956e83a944df1c54e4be3554f2ed4863ebe2f75</id>
<content type='text'>
We can have multiple matching DT nodes of the same FDT ipi driver
so in this case we should call cold_init() for all matching DT nodes
instead of just first matching DT node.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atish.patra@wdc.com&gt;
</content>
</entry>
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