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<title>opensbi.git/platform/fpga, branch master</title>
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<updated>2025-11-05T15:52:41Z</updated>
<entry>
<title>platform: ariane: Move ariane platform from fpga to generic</title>
<updated>2025-11-05T15:52:41Z</updated>
<author>
<name>Manuel Hernández Méndez</name>
<email>maherme.dev@gmail.com</email>
</author>
<published>2025-10-23T09:03:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=e8dfa55f3d6ada2e1f71671213bd3a68ec96ea76'/>
<id>urn:sha1:e8dfa55f3d6ada2e1f71671213bd3a68ec96ea76</id>
<content type='text'>
The Ariane framework has a generic PMU that is not used by OpenSBI.
Due to OpenSBI’s build system we cannot directly reuse the generic
platform functions, so move the Ariane platform to generic. Also due
to the generic platform is where new features are added.

Signed-off-by: Manuel Hernández Méndez &lt;maherme.dev@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20251023090347.30746-1-maherme.dev@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>include: sbi: Remove platform specific IPI init</title>
<updated>2025-09-16T04:26:31Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2025-09-04T05:24:09Z</published>
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<id>urn:sha1:85f22b38c8b8c00812b0ea277ac212d82d169b9e</id>
<content type='text'>
The platform specfic IPI init is not need anymore because using
IPI device rating multiple IPI devices can be registered in any
order as part of the platform specific early init.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Tested-by: Nick Hu &lt;nick.hu@sifive.com&gt;
Link: https://lore.kernel.org/r/20250904052410.546818-3-apatel@ventanamicro.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: openpiton: Move openpiton platform from fpga to generic</title>
<updated>2025-08-26T11:38:00Z</updated>
<author>
<name>Manuel Hernández Méndez</name>
<email>maherme.dev@gmail.com</email>
</author>
<published>2025-08-13T10:47:59Z</published>
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<id>urn:sha1:525ac970b3c2b1549c8747959cfc4f9b84e1f711</id>
<content type='text'>
The OpenPiton framework has a generic PMU that is not used by OpenSBI.
Due to OpenSBI’s build system we cannot directly reuse the generic
platform functions, so move the OpenPiton platform to generic. Also due
to the generic platform is where new features are added.

Signed-off-by: Manuel Hernández Méndez &lt;maherme.dev@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250813104759.33276-1-maherme.dev@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: openpiton: fix uninitialized plic_data struct</title>
<updated>2025-07-22T09:56:44Z</updated>
<author>
<name>Manuel Hernández Méndez</name>
<email>maherme.dev@gmail.com</email>
</author>
<published>2025-07-08T18:09:14Z</published>
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<id>urn:sha1:0b7c2e0d6091e6f48b4b3b2a345fd588eb95ddfc</id>
<content type='text'>
The plic_data struct was uninitialized. This led to misfunction behavior
since it was subsequently assigned to the global plic struct, and some
struct fields, such as flags and irqchip, contained random values.
The fix proposes to initialize the plic_data to the global plic struct,
so, after parsing the fdt, the fields of the struct will be set to the
default values set in global plic struct definition, or the parsed values
in the fdt, or zero.

Fixes: 4c37451 ("platform: openpiton: Read the device configurations from device tree")
Signed-off-by: Manuel Hernández Méndez &lt;maherme.dev@gmail.com&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250708180914.1131-1-maherme.dev@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/serial: Add PXA UARTs support</title>
<updated>2025-03-27T14:50:05Z</updated>
<author>
<name>Junhui Liu</name>
<email>junhui.liu@pigmoral.tech</email>
</author>
<published>2025-03-27T06:48:18Z</published>
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<id>urn:sha1:8fe835303c4c7d134f07002c234ec5ec637953ca</id>
<content type='text'>
The PXA variant of the uart8250 adds the UART Unit Enable bit (UUE) that
needs to be set to enable the XScale PXA UART. And it is required for
some RISC-V SoCs like the Spacemit K1 that implement the PXA UART.

This introduces the "intel,xscale-uart" compatible to handle setting the
UUE bit.

Signed-off-by: Junhui Liu &lt;junhui.liu@pigmoral.tech&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20250327-pxa-uart-support-v2-1-c4400c1fcd0b@pigmoral.tech
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>platform: Drop irqchip warm init and exit hooks</title>
<updated>2024-11-28T06:16:36Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:09Z</published>
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<id>urn:sha1:678f5909a3fe54d528276f9afce5dd3148e42cbf</id>
<content type='text'>
Now that driver lifecycle is managed from within the SBI irqchip core,
platforms need only to initialize the driver once during cold init.
Remove the remaining platform hooks that are no longer used.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi_irqchip: Call driver warm_init from SBI core</title>
<updated>2024-11-28T06:10:17Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=2dd6eaf680556e763a85b0b4ae180391e2671854'/>
<id>urn:sha1:2dd6eaf680556e763a85b0b4ae180391e2671854</id>
<content type='text'>
Currently, each platform keeps track of which irqchip driver is in use
and calls its warm init function. Since the generic platform may use
multiple irqchip drivers, it has logic to track an array of drivers.

The code is simplified and made common across platforms by treating warm
init and exit as properties of the driver, not the platform. Then the
platform's only role is to select and prepare a driver during cold boot.

For now, only add a .warm_init hook, since none of the existing drivers
need an .exit hook. It could be added in the future if needed.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: Move per-hart data from fdt_plic to plic</title>
<updated>2024-11-28T06:05:01Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=56fddce83f163e5e90ea82bf78a8df3d990b0572'/>
<id>urn:sha1:56fddce83f163e5e90ea82bf78a8df3d990b0572</id>
<content type='text'>
The per-hart PLIC pointer is not really specific to FDT platforms. Move
it into the main driver and drop the extra wrapper functions.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: plic: Provide a hartindex to context map</title>
<updated>2024-11-28T04:06:46Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:04Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=69448a07906523c9c798c8f1d02a7be52e96b38e'/>
<id>urn:sha1:69448a07906523c9c798c8f1d02a7be52e96b38e</id>
<content type='text'>
This removes platform-specific arguments to plic_warm_irqchip_init(),
which makes the driver independent from the platform after cold init,
and allows for further refactoring.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/irqchip: plic: Allow enabling IRQs by default</title>
<updated>2024-11-28T04:05:10Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel.holland@sifive.com</email>
</author>
<published>2024-11-05T04:10:02Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/opensbi.git/commit/?id=a786aed08dbc20368426970eaf393867ec88b940'/>
<id>urn:sha1:a786aed08dbc20368426970eaf393867ec88b940</id>
<content type='text'>
Unlike other platforms, Ariane and OpenPiton enable all IRQs by default.
This was described in commit b44e844880d0 ("Add support for Ariane FPGA
SoC") as "due to some issue of the design." Add this workaround behind a
flag in plic_warm_irqchip_init(), so every platform can use the same
warm init function.

Signed-off-by: Samuel Holland &lt;samuel.holland@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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