opensbi.git/platform/generic/Kconfig, branch v1.4

platform: rzfive: Enable Andes PMU for RZ/Five

2023-12-06T12:27:28Z

Enable Andes PMU extension support for RZ/Five. We also staticize renesas_rzfive_early_init() as it is not used outside of this unit. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Atish Patra Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar Reviewed-by: Anup Patel

platform: andes: Enable Andes PMU for AE350

2023-12-06T12:25:55Z

Enable Andes PMU extension support for AE350 platforms. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Atish Patra Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar Reviewed-by: Anup Patel

platform: generic: Add Sophgo sg2042 platform support

2023-11-16T15:52:27Z

Add Sophgo sg2042 soc support Signed-off-by: Inochi Amaoto Reviewed-by: Guo Ren Reviewed-by: Anup Patel

platform: generic: thead: initialize PMU by default in thead generic platform

2023-11-14T16:23:52Z

Since all the SoC with thead c9xx cores need this initialization at now, initialize the c9xx pmu in the thead generic platform by default. Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel

platform: generic: thead: separate implement of T-HEAD c9xx errata

2023-11-14T16:23:50Z

Separate the implement of T-HEAD c9xx errata to allow any platform with bug related to c9xx cores can use it. Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel

platform: generic: thead: separate implement of T-HEAD c9xx pmu

2023-11-14T16:23:45Z

Separate the implement of T-HEAD c9xx pmu to allow any platform with c9xx cores can use it. Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel

platform: generic: thead: fix stale TLB entries for th1520/sg2042

2023-10-04T13:29:54Z

The TLB entries remain functional all the time once added in T-HEAD th1520 and Sophgo sg2042 (even if the MMU is then disabled afterwards). If there are some stale TLB entries that contains the address of SBI, it will cause unexpected memory access and issue a illegal instruction error. To avoid this, a TLB flush is needed to drop these TLB entries before any memory access in the trap handler. To handle this workaroud, add a custom trap handler with executing TLB flush first in the T-HEAD platform to fix affected socs. Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel

platform: generic: andes/renesas: Add SBI EXT to check for enabling IOCP errata

2023-04-14T12:05:04Z

platform: generic: renesas: rzfive: Configure the PMA region

2023-02-27T06:06:06Z

On the Renesas RZ/Five SoC by default we want to configure 128MiB of memory ranging from 0x58000000 as a non-cacheable + bufferable region in the PMA and populate this region as PMA reserve DT node with shared DMA pool and no-map flags set so that Linux drivers requesting any DMA'able memory go through this region. PMA node passed to the above stack: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar Reviewed-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

platform: generic: renesas: rzfive: Add support to configure the PMA

2023-02-27T06:05:01Z

I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason IP blocks using DMA will fail. The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) block that allows dynamic adjustment of memory attributes in the runtime. It contains a configurable amount of PMA entries implemented as CSR registers to control the attributes of memory locations in interest. Below are the memory attributes supported: * Device, Non-bufferable * Device, bufferable * Memory, Non-cacheable, Non-bufferable * Memory, Non-cacheable, Bufferable * Memory, Write-back, No-allocate * Memory, Write-back, Read-allocate * Memory, Write-back, Write-allocate * Memory, Write-back, Read and Write-allocate More info about PMA (section 10.3): Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. Example PMA region passed as a DT node from OpenSBI: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar Reviewed-by: Yu Chien Peter Lin Reviewed-by: Anup Patel