opensbi.git/platform/generic/Kconfig, branch v1.7

platform: generic: mips: add P8700

2025-06-14T16:14:11Z

Extend generic platform to support MIPS P8700. Signed-off-by: Chao-ying Fu Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20250522212141.3198-2-cfu@mips.com Signed-off-by: Anup Patel

platform: generic: Kconfig: add the description for Andes PMA feature

2024-08-23T08:33:45Z

Describe Andes PPMA in the config option, and select it for AE350 platform. Signed-off-by: Ben Zong-You Xie Reviewed-by: Anup Patel

platform: andes: Change all occurrences of andes45 to andes

2024-05-09T12:27:51Z

To make the framework suit all Andes CPUs, change all occurrences of andes45 to andes. In addition, we fix some coding style problems and remove an unused macro in andes.h. Signed-off-by: Ben Zong-You Xie Reviewed-by: Anup Patel

platform: rzfive: Enable Andes PMU for RZ/Five

2023-12-06T12:27:28Z

Enable Andes PMU extension support for RZ/Five. We also staticize renesas_rzfive_early_init() as it is not used outside of this unit. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Atish Patra Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar Reviewed-by: Anup Patel

platform: andes: Enable Andes PMU for AE350

2023-12-06T12:25:55Z

Enable Andes PMU extension support for AE350 platforms. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Atish Patra Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar Reviewed-by: Anup Patel

platform: generic: Add Sophgo sg2042 platform support

2023-11-16T15:52:27Z

Add Sophgo sg2042 soc support Signed-off-by: Inochi Amaoto Reviewed-by: Guo Ren Reviewed-by: Anup Patel

platform: generic: thead: initialize PMU by default in thead generic platform

2023-11-14T16:23:52Z

Since all the SoC with thead c9xx cores need this initialization at now, initialize the c9xx pmu in the thead generic platform by default. Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel

platform: generic: thead: separate implement of T-HEAD c9xx errata

2023-11-14T16:23:50Z

Separate the implement of T-HEAD c9xx errata to allow any platform with bug related to c9xx cores can use it. Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel

platform: generic: thead: separate implement of T-HEAD c9xx pmu

2023-11-14T16:23:45Z

Separate the implement of T-HEAD c9xx pmu to allow any platform with c9xx cores can use it. Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel

platform: generic: thead: fix stale TLB entries for th1520/sg2042

2023-10-04T13:29:54Z

The TLB entries remain functional all the time once added in T-HEAD th1520 and Sophgo sg2042 (even if the MMU is then disabled afterwards). If there are some stale TLB entries that contains the address of SBI, it will cause unexpected memory access and issue a illegal instruction error. To avoid this, a TLB flush is needed to drop these TLB entries before any memory access in the trap handler. To handle this workaroud, add a custom trap handler with executing TLB flush first in the T-HEAD platform to fix affected socs. Signed-off-by: Inochi Amaoto Reviewed-by: Anup Patel