opensbi.git/platform/generic/allwinner, branch v1.3

platform: generic/allwinner: Fix sun20i-d1.c header dependency

2023-02-27T04:30:15Z

The code calls various macros from riscv_asm.h and sbi_scratch.h which are not directly included. Fix such dependency. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

platform: generic: allwinner: Advertise nonretentive suspend

2023-01-24T12:00:21Z

Add D1's nonretentive suspend state to the devicetree so S-mode software knows about it and can use it. Latency and power measurements were taken on an Allwinner Nezha board: - Entry latency was measured from the beginning of sbi_ecall_handler() to before the call to wfi() in sun20i_d1_hart_suspend(). - Exit latency was measured from the beginning of sbi_init() to before the call to sbi_hart_switch_mode() in init_warmboot(). - There was a 17.5 mW benefit from non-retentive suspend compared to WFI, with a 170 mW cost during the 107 us entry/exit period. This provides a break-even point around 1040 us. Residency includes entry latency, so round this up to 1100 us. - The hardware power sequence latency (after the WFI) is assumed to be negligible, so set the wakeup latency to the exit latency. Reviewed-by: Anup Patel Signed-off-by: Samuel Holland

platform: generic: allwinner: Fix PLIC array bounds

2023-01-13T12:09:42Z

The two referenced commits passed incorrect bounds to the PLIC save/ restore functions, causing out-of-bounds memory access. The functions expect "num" to be the 1-based number of interrupt sources, equivalent to the "riscv,ndev" devicetree property. Thus, "num" must be strictly smaller than the 0-based size of the array storing the register values. However, the referenced commits incorrectly passed in the unmodified size of the array as "num". Fix this by reducing PLIC_SOURCES (matching "riscv,ndev" on this platform), while keeping the same array sizes. Addresses-Coverity-ID: 1530251 ("Out-of-bounds access") Addresses-Coverity-ID: 1530252 ("Out-of-bounds access") Fixes: 8509e46ca63a ("lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers") Fixes: 9a2eeb4aaeac ("lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers") Signed-off-by: Samuel Holland Reviewed-by: Anup Patel

lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers

2022-12-17T03:33:30Z

Currently the context save/restore helpers writes/reads the provided array using an index whose maximum value is determined by PLIC, which potentially may disagree with the caller to these helpers. Add a parameter to ask the caller to provide the size limit of the array to ensure no out-of-bound access happens. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers

2022-12-17T03:30:29Z

Currently the priority save/restore helpers writes/reads the provided array using an index whose maximum value is determined by PLIC, which potentially may disagree with the caller to these helpers. Add a parameter to ask the caller to provide the size limit of the array to ensure no out-of-bound access happens. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

platform: generic/allwinner: Remove ghostly type cast

2022-12-04T15:08:46Z

Corrected the same parameter of writel_relaxed in sun20i_d1_riscv_cfg_init to be u32 for a while and u64 for a while. Signed-off-by: Xiang W Reviewed-by: Anup Patel

platform: generic/allwinner: Remove unused header files

2022-11-22T06:16:19Z

Remove "#include " Signed-off-by: Leizheng Zhang Reviewed-by: Bin Meng Reviewed-by: Xiang W

platform: generic: allwinner: add support for c9xx pmu

2022-10-13T04:22:09Z

With the T-HEAD C9XX cores being designed before or during ratification of the SSCOFPMF extension, they implement a PMU extension that behaves very similar but not equal to it by providing overflow interrupts though in a slightly different registers format. The sun20i-d1 is using this core. So implement the necessary overrides to allow its pmu to be used via the standard sbi-pmu extension. For now it's also the only soc using this core, so keep the additional code in the d1-space for now. Reviewed-by: Andrew Jones Reviewed-by: Guo Ren Reviewed-by: Anup Patel Signed-off-by: Heiko Stuebner

platform: generic: Use kconfig for enabling/disabling overrides

2022-08-08T04:04:14Z

We update generic platform to use kconfig for enabling/disabling platform overrides. We also enable all platform overrides in generic platform defconfig. Signed-off-by: Anup Patel Tested-by: Andrew Jones Acked-by: Atish Patra Tested-by: Atish Patra

platform: Add HSM implementation for Allwinner D1

2022-06-13T06:29:09Z

Allwinner D1 contains a "PPU" power domain controller which can automatically power down/up the CPU power domain. This power domain includes the C906 core along with its CLINT and PLIC. This HSM implementation supports non-retentive hart suspend by: 1) Saving/restoring state that is lost during hart suspend, 2) Performing cache maintenance before/after hart suspend, 3) Configuring wakeup sources before hart suspend, and 4) Asking the PPU to power down the hart when it enters WFI. Since this HSM implementation is for a single-core SoC, it does not need to worry about concurrency or saving multiple instances of state. Reviewed-by: Anup Patel Signed-off-by: Samuel Holland